--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.39
--  \   \         Application: netgen
--  /   /         Filename: I2CmasterDemo_synthesis.vhd
-- /___/   /\     Timestamp: Fri Jan 22 00:52:39 2010
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -ar Structure -tm I2CmasterDemo -w -dir netgen/synthesis -ofmt vhdl -sim I2CmasterDemo.ngc I2CmasterDemo_synthesis.vhd 
-- Device	: xc3s250e-4-pq208
-- Input file	: I2CmasterDemo.ngc
-- Output file	: C:\Documents and Settings\sxs5464\Desktop\RapidFPGA\code\Xilinx Projects\ImagerController\netgen\synthesis\I2CmasterDemo_synthesis.vhd
-- # of Entities	: 1
-- Design Name	: I2CmasterDemo
-- Xilinx	: C:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity I2CmasterDemo_synth is
  port (
    I2C_Data : inout STD_LOGIC; 
    I2C_Clk : out STD_LOGIC; 
    SW : in STD_LOGIC; 
    FPGA_Clk : in STD_LOGIC := 'X' 
  );
end I2CmasterDemo_synth;

architecture Structure of I2CmasterDemo_synth is
  signal CLK_Mcount_clk_div_cy_1_rt_2 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_2_rt_4 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_3_rt_6 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_4_rt_8 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_5_rt_10 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_6_rt_12 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_xor_7_rt_14 : STD_LOGIC; 
  signal CLK_sI2C_Clk_23 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq0000 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq000016_25 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq00007_26 : STD_LOGIC; 
  signal CLK_sI2C_Clk_not0001 : STD_LOGIC; 
  signal FPGA_Clk_BUFGP_29 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal N104 : STD_LOGIC; 
  signal N106 : STD_LOGIC; 
  signal N108 : STD_LOGIC; 
  signal N119 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N121 : STD_LOGIC; 
  signal N125 : STD_LOGIC; 
  signal N127 : STD_LOGIC; 
  signal N128 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal N132 : STD_LOGIC; 
  signal N134 : STD_LOGIC; 
  signal N136 : STD_LOGIC; 
  signal N138 : STD_LOGIC; 
  signal N140 : STD_LOGIC; 
  signal N142 : STD_LOGIC; 
  signal N143 : STD_LOGIC; 
  signal N145 : STD_LOGIC; 
  signal N149 : STD_LOGIC; 
  signal N150 : STD_LOGIC; 
  signal N151 : STD_LOGIC; 
  signal N152 : STD_LOGIC; 
  signal N153 : STD_LOGIC; 
  signal N154 : STD_LOGIC; 
  signal N155 : STD_LOGIC; 
  signal N156 : STD_LOGIC; 
  signal N157 : STD_LOGIC; 
  signal N158 : STD_LOGIC; 
  signal N159 : STD_LOGIC; 
  signal N160 : STD_LOGIC; 
  signal N161 : STD_LOGIC; 
  signal N162 : STD_LOGIC; 
  signal N163 : STD_LOGIC; 
  signal N164 : STD_LOGIC; 
  signal N165 : STD_LOGIC; 
  signal N166 : STD_LOGIC; 
  signal N167 : STD_LOGIC; 
  signal N168 : STD_LOGIC; 
  signal N169 : STD_LOGIC; 
  signal N170 : STD_LOGIC; 
  signal N171 : STD_LOGIC; 
  signal N172 : STD_LOGIC; 
  signal N173 : STD_LOGIC; 
  signal N174 : STD_LOGIC; 
  signal N175 : STD_LOGIC; 
  signal N176 : STD_LOGIC; 
  signal N177 : STD_LOGIC; 
  signal N178 : STD_LOGIC; 
  signal N179 : STD_LOGIC; 
  signal N180 : STD_LOGIC; 
  signal N181 : STD_LOGIC; 
  signal N182 : STD_LOGIC; 
  signal N183 : STD_LOGIC; 
  signal N184 : STD_LOGIC; 
  signal N185 : STD_LOGIC; 
  signal N186 : STD_LOGIC; 
  signal N187 : STD_LOGIC; 
  signal N188 : STD_LOGIC; 
  signal N189 : STD_LOGIC; 
  signal N190 : STD_LOGIC; 
  signal N191 : STD_LOGIC; 
  signal N192 : STD_LOGIC; 
  signal N193 : STD_LOGIC; 
  signal N194 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal N27 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal N35 : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal N43 : STD_LOGIC; 
  signal N45 : STD_LOGIC; 
  signal N47 : STD_LOGIC; 
  signal N49 : STD_LOGIC; 
  signal N51 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal N62 : STD_LOGIC; 
  signal N64 : STD_LOGIC; 
  signal N68 : STD_LOGIC; 
  signal N70 : STD_LOGIC; 
  signal N71 : STD_LOGIC; 
  signal N73 : STD_LOGIC; 
  signal N74 : STD_LOGIC; 
  signal N76 : STD_LOGIC; 
  signal N77 : STD_LOGIC; 
  signal N79 : STD_LOGIC; 
  signal N81 : STD_LOGIC; 
  signal N83 : STD_LOGIC; 
  signal N87 : STD_LOGIC; 
  signal N89 : STD_LOGIC; 
  signal N90 : STD_LOGIC; 
  signal N91 : STD_LOGIC; 
  signal N93 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal SW_IBUF_142 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_145 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_not0001 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_147 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_and00001 : STD_LOGIC; 
  signal UUT_Dir_149 : STD_LOGIC; 
  signal UUT_Dir_mux000011_150 : STD_LOGIC; 
  signal UUT_Dir_mux0000127_151 : STD_LOGIC; 
  signal UUT_Dir_mux0000143_152 : STD_LOGIC; 
  signal UUT_Dir_mux0000148_153 : STD_LOGIC; 
  signal UUT_Dir_mux0000224 : STD_LOGIC; 
  signal UUT_Dir_mux000058_155 : STD_LOGIC; 
  signal UUT_Dir_mux000061 : STD_LOGIC; 
  signal UUT_Dir_mux000082_157 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_10_rt_160 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_1_rt_162 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_2_rt_164 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_3_rt_166 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_4_rt_168 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_5_rt_170 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_6_rt_172 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_7_rt_174 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_8_rt_176 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_9_rt_178 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_xor_11_rt_180 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_10_rt_184 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_11_rt_186 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_12_rt_188 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_13_rt_190 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_14_rt_192 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_1_rt_194 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_2_rt_196 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_3_rt_198 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_4_rt_200 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_5_rt_202 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_6_rt_204 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_7_rt_206 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_8_rt_208 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_9_rt_210 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_xor_15_rt_212 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_10_rt_215 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_11_rt_217 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_12_rt_219 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_13_rt_221 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_14_rt_223 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_15_rt_225 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_16_rt_227 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_17_rt_229 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_18_rt_231 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_19_rt_233 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_1_rt_235 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_20_rt_237 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_21_rt_239 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_22_rt_241 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_23_rt_243 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_24_rt_245 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_25_rt_247 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_26_rt_249 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_27_rt_251 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_28_rt_253 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_29_rt_255 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_2_rt_257 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_3_rt_259 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_4_rt_261 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_5_rt_263 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_6_rt_265 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_7_rt_267 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_8_rt_269 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_cy_9_rt_271 : STD_LOGIC; 
  signal UUT_Madd_writeCount_share0000_xor_30_rt_273 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_0_rt_275 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_4_rt_280 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_283 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_284 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_286 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_287 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_0_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_2_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_298 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_300 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_302 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_304 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_0_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_0_rt_310 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_2_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_rt_315 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_4_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_323 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_2_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_4_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_331 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_334 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_cmp_eq0000 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_cmp_eq0003_336 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux0000 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000011_338 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000022_339 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000037_340 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000065_341 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000078_342 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000088_343 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001134_345 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001137_346 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001162_347 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001176_348 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000137_349 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000155_350 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000178_351 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000185_352 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_353 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux0000 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000012_355 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000024_356 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000062_357 : STD_LOGIC; 
  signal UUT_N0 : STD_LOGIC; 
  signal UUT_N11 : STD_LOGIC; 
  signal UUT_N12 : STD_LOGIC; 
  signal UUT_N121 : STD_LOGIC; 
  signal UUT_N13 : STD_LOGIC; 
  signal UUT_N14 : STD_LOGIC; 
  signal UUT_N15 : STD_LOGIC; 
  signal UUT_N211 : STD_LOGIC; 
  signal UUT_N26 : STD_LOGIC; 
  signal UUT_N27 : STD_LOGIC; 
  signal UUT_N3 : STD_LOGIC; 
  signal UUT_N31 : STD_LOGIC; 
  signal UUT_N3106_370 : STD_LOGIC; 
  signal UUT_N3157_371 : STD_LOGIC; 
  signal UUT_N3178_372 : STD_LOGIC; 
  signal UUT_N32 : STD_LOGIC; 
  signal UUT_N320_374 : STD_LOGIC; 
  signal UUT_N327_375 : STD_LOGIC; 
  signal UUT_N33_376 : STD_LOGIC; 
  signal UUT_N331 : STD_LOGIC; 
  signal UUT_N332 : STD_LOGIC; 
  signal UUT_N349_379 : STD_LOGIC; 
  signal UUT_N35 : STD_LOGIC; 
  signal UUT_N351 : STD_LOGIC; 
  signal UUT_N362_382 : STD_LOGIC; 
  signal UUT_N38 : STD_LOGIC; 
  signal UUT_N392_384 : STD_LOGIC; 
  signal UUT_N4 : STD_LOGIC; 
  signal UUT_N41 : STD_LOGIC; 
  signal UUT_N42 : STD_LOGIC; 
  signal UUT_N45 : STD_LOGIC; 
  signal UUT_N53 : STD_LOGIC; 
  signal UUT_N55 : STD_LOGIC; 
  signal UUT_N60 : STD_LOGIC; 
  signal UUT_N62 : STD_LOGIC; 
  signal UUT_N64 : STD_LOGIC; 
  signal UUT_N67 : STD_LOGIC; 
  signal UUT_N68 : STD_LOGIC; 
  signal UUT_N70 : STD_LOGIC; 
  signal UUT_N72 : STD_LOGIC; 
  signal UUT_ack_count_and0025 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_23_411 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_39_412 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_56_413 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_73 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_212_416 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_11 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_24_449 : STD_LOGIC; 
  signal UUT_delay_count_and0000 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_0_467 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_117_468 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_122_469 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_146_470 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_18_471 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_181_472 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_25 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_6_474 : STD_LOGIC; 
  signal UUT_delay_count_or0000 : STD_LOGIC; 
  signal UUT_delay_count_or0001 : STD_LOGIC; 
  signal UUT_in_i2c : STD_LOGIC; 
  signal UUT_nstate_FFd1_509 : STD_LOGIC; 
  signal UUT_nstate_FFd1_In33 : STD_LOGIC; 
  signal UUT_nstate_FFd2_511 : STD_LOGIC; 
  signal UUT_nstate_FFd2_In1_512 : STD_LOGIC; 
  signal UUT_nstate_FFd3_513 : STD_LOGIC; 
  signal UUT_nstate_FFd3_In_514 : STD_LOGIC; 
  signal UUT_nstate_FFd4_515 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In0_516 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In37_517 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In77_518 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In79 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0000_520 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0001 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0005 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0006 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0008 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0010 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0011 : STD_LOGIC; 
  signal UUT_out_i2c : STD_LOGIC; 
  signal UUT_out_i2cclk_528 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000115_529 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000142_530 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000145_531 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000017_532 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000186_533 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux00002 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000020_535 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000021_536 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000210_537 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000213_538 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000237_539 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000270_540 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000296 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000055_542 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000071_543 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000083_544 : STD_LOGIC; 
  signal UUT_prevClk_545 : STD_LOGIC; 
  signal UUT_prevClk_mux0000 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1110_550 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1111_551 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1143_552 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1180_553 : STD_LOGIC; 
  signal UUT_shiftReg_and0000 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0000 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0002 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_110_582 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_113_583 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_116_584 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_216_585 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_23 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_240_587 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_25_588 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_5_589 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_8_590 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_1_1_591 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_0_592 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_11 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_3_594 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_23 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_5_596 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_8_597 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_0_598 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_11 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_3_600 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_1_601 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_18 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_3_603 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_5_604 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_7_1_605 : STD_LOGIC; 
  signal UUT_shiftReg_or0000 : STD_LOGIC; 
  signal UUT_shiftReg_or000012_607 : STD_LOGIC; 
  signal UUT_shiftReg_or000017_608 : STD_LOGIC; 
  signal UUT_shiftReg_or000032_609 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal CLK_Mcount_clk_div_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal CLK_clk_div : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_ClkEdge : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal UUT_Madd_ack_count_share0000_cy : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal UUT_Madd_ack_count_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Madd_counter_addsub0000_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal UUT_Madd_delay_count_share0000_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal UUT_Madd_delay_count_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Madd_writeCount_share0000_cy : STD_LOGIC_VECTOR ( 29 downto 0 ); 
  signal UUT_Madd_writeCount_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_ack_count : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal UUT_ack_count_mux0000 : STD_LOGIC_VECTOR ( 11 downto 1 ); 
  signal UUT_ack_count_share0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal UUT_counter : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal UUT_counter_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal UUT_delay_count : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal UUT_delay_count_mux0000 : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal UUT_delay_count_share0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal UUT_pstate : STD_LOGIC_VECTOR ( 3 downto 2 ); 
  signal UUT_pstate_mux0000 : STD_LOGIC_VECTOR ( 6 downto 5 ); 
  signal UUT_shiftReg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_shiftReg_cmp_eq0001_wg_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal UUT_shiftReg_cmp_eq0001_wg_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_writeCount : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal UUT_writeCount_mux0000 : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal UUT_writeCount_share0000 : STD_LOGIC_VECTOR ( 30 downto 0 ); 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  CLK_sI2C_Clk : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      CE => CLK_sI2C_Clk_cmp_eq0000,
      D => CLK_sI2C_Clk_not0001,
      Q => CLK_sI2C_Clk_23
    );
  CLK_clk_div_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(0),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(0)
    );
  CLK_clk_div_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(1),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(1)
    );
  CLK_clk_div_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(2),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(2)
    );
  CLK_clk_div_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(3),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(3)
    );
  CLK_clk_div_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(4),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(4)
    );
  CLK_clk_div_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(5),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(5)
    );
  CLK_clk_div_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(6),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(6)
    );
  CLK_clk_div_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => Result(7),
      R => CLK_sI2C_Clk_cmp_eq0000,
      Q => CLK_clk_div(7)
    );
  CLK_Mcount_clk_div_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => CLK_Mcount_clk_div_lut(0),
      O => CLK_Mcount_clk_div_cy(0)
    );
  CLK_Mcount_clk_div_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => CLK_Mcount_clk_div_lut(0),
      O => Result(0)
    );
  CLK_Mcount_clk_div_cy_1_Q : MUXCY
    port map (
      CI => CLK_Mcount_clk_div_cy(0),
      DI => N0,
      S => CLK_Mcount_clk_div_cy_1_rt_2,
      O => CLK_Mcount_clk_div_cy(1)
    );
  CLK_Mcount_clk_div_xor_1_Q : XORCY
    port map (
      CI => CLK_Mcount_clk_div_cy(0),
      LI => CLK_Mcount_clk_div_cy_1_rt_2,
      O => Result(1)
    );
  CLK_Mcount_clk_div_cy_2_Q : MUXCY
    port map (
      CI => CLK_Mcount_clk_div_cy(1),
      DI => N0,
      S => CLK_Mcount_clk_div_cy_2_rt_4,
      O => CLK_Mcount_clk_div_cy(2)
    );
  CLK_Mcount_clk_div_xor_2_Q : XORCY
    port map (
      CI => CLK_Mcount_clk_div_cy(1),
      LI => CLK_Mcount_clk_div_cy_2_rt_4,
      O => Result(2)
    );
  CLK_Mcount_clk_div_cy_3_Q : MUXCY
    port map (
      CI => CLK_Mcount_clk_div_cy(2),
      DI => N0,
      S => CLK_Mcount_clk_div_cy_3_rt_6,
      O => CLK_Mcount_clk_div_cy(3)
    );
  CLK_Mcount_clk_div_xor_3_Q : XORCY
    port map (
      CI => CLK_Mcount_clk_div_cy(2),
      LI => CLK_Mcount_clk_div_cy_3_rt_6,
      O => Result(3)
    );
  CLK_Mcount_clk_div_cy_4_Q : MUXCY
    port map (
      CI => CLK_Mcount_clk_div_cy(3),
      DI => N0,
      S => CLK_Mcount_clk_div_cy_4_rt_8,
      O => CLK_Mcount_clk_div_cy(4)
    );
  CLK_Mcount_clk_div_xor_4_Q : XORCY
    port map (
      CI => CLK_Mcount_clk_div_cy(3),
      LI => CLK_Mcount_clk_div_cy_4_rt_8,
      O => Result(4)
    );
  CLK_Mcount_clk_div_cy_5_Q : MUXCY
    port map (
      CI => CLK_Mcount_clk_div_cy(4),
      DI => N0,
      S => CLK_Mcount_clk_div_cy_5_rt_10,
      O => CLK_Mcount_clk_div_cy(5)
    );
  CLK_Mcount_clk_div_xor_5_Q : XORCY
    port map (
      CI => CLK_Mcount_clk_div_cy(4),
      LI => CLK_Mcount_clk_div_cy_5_rt_10,
      O => Result(5)
    );
  CLK_Mcount_clk_div_cy_6_Q : MUXCY
    port map (
      CI => CLK_Mcount_clk_div_cy(5),
      DI => N0,
      S => CLK_Mcount_clk_div_cy_6_rt_12,
      O => CLK_Mcount_clk_div_cy(6)
    );
  CLK_Mcount_clk_div_xor_6_Q : XORCY
    port map (
      CI => CLK_Mcount_clk_div_cy(5),
      LI => CLK_Mcount_clk_div_cy_6_rt_12,
      O => Result(6)
    );
  CLK_Mcount_clk_div_xor_7_Q : XORCY
    port map (
      CI => CLK_Mcount_clk_div_cy(6),
      LI => CLK_Mcount_clk_div_xor_7_rt_14,
      O => Result(7)
    );
  UUT_IOBUF_inst : IOBUF
    generic map(
      CAPACITANCE => "DONT_CARE",
      DRIVE => 12,
      IBUF_DELAY_VALUE => "0",
      IFD_DELAY_VALUE => "AUTO",
      IOSTANDARD => "DEFAULT"
    )
    port map (
      I => UUT_in_i2c,
      T => UUT_Dir_149,
      O => UUT_out_i2c,
      IO => I2C_Data
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_Q : MUXCY
    port map (
      CI => UUT_Mcompar_delay_count_cmp_lt0000_cy(5),
      DI => N1,
      S => UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_287,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy(6)
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_delay_count(13),
      I1 => UUT_delay_count(14),
      I2 => UUT_delay_count(15),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_287
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_Q : MUXCY
    port map (
      CI => UUT_Mcompar_delay_count_cmp_lt0000_cy(4),
      DI => N1,
      S => UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_286,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy(5)
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(10),
      I2 => UUT_delay_count(11),
      I3 => UUT_delay_count(12),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_286
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_4_Q : MUXCY
    port map (
      CI => UUT_Mcompar_delay_count_cmp_lt0000_cy(3),
      DI => N0,
      S => UUT_Mcompar_delay_count_cmp_lt0000_cy_4_rt_280,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy(4)
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_Q : MUXCY
    port map (
      CI => UUT_Mcompar_delay_count_cmp_lt0000_cy(2),
      DI => N1,
      S => UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy(3)
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_2_Q : MUXCY
    port map (
      CI => UUT_Mcompar_delay_count_cmp_lt0000_cy(1),
      DI => N0,
      S => UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_284,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy(2)
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_delay_count(5),
      I1 => UUT_delay_count(6),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_284
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_Q : MUXCY
    port map (
      CI => UUT_Mcompar_delay_count_cmp_lt0000_cy(0),
      DI => N1,
      S => UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_283,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy(1)
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => UUT_delay_count(3),
      I1 => UUT_delay_count(4),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_283
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => UUT_Mcompar_delay_count_cmp_lt0000_cy_0_rt_275,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy(0)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy(6),
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(7),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(7)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_6_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(6),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(6)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_6_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_delay_count(11),
      I1 => UUT_delay_count(12),
      I2 => UUT_delay_count(13),
      I3 => UUT_delay_count(14),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(6)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy_4_1,
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_331,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_5_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(10),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_331
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_4_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut_4_1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_4_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy_2_1,
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(3),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_3_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_delay_count(6),
      I1 => UUT_delay_count(7),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(3)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_2_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut_2_1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_2_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy_0_1,
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0002_cy_1_0_rt_310,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_0_0 : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_323,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_0_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_0_1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => UUT_delay_count(2),
      I1 => UUT_delay_count(3),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_323
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy(4),
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(5),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(5)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_5_Q : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_delay_count(13),
      I1 => UUT_delay_count(14),
      I2 => UUT_delay_count(15),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(5)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_4_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy(3),
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(4),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(4)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_4_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(10),
      I2 => UUT_delay_count(11),
      I3 => UUT_delay_count(12),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(4)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy(2),
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0002_cy_3_rt_315,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(3)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_2_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy(1),
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(2),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(2)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0002_cy(0),
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(1),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(1)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_1_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_delay_count(5),
      I1 => UUT_delay_count(6),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(1)
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0002_lut(0),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy(0)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_0_Q : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_delay_count(2),
      I1 => UUT_delay_count(3),
      I2 => UUT_delay_count(4),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(0)
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0000_cy_2_1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_304,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_3_1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => UUT_ack_count(10),
      I1 => UUT_ack_count(11),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_304
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_2_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_302,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_2_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_2_1 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(7),
      I2 => UUT_ack_count(8),
      I3 => UUT_ack_count(9),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_302
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_0 : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0000_cy_0_1,
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_300,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_1_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_ack_count(4),
      I1 => UUT_ack_count(5),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_300
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_0_0 : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_298,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_0_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_0_1 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(0),
      I1 => UUT_ack_count(1),
      I2 => UUT_ack_count(2),
      I3 => UUT_ack_count(3),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_298
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0000_cy(3),
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut(4),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy(4)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_4_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(8),
      I1 => UUT_ack_count(9),
      I2 => UUT_ack_count(10),
      I3 => UUT_ack_count(11),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(4)
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0000_cy(2),
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut(3),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy(3)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_3_Q : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count(6),
      I2 => UUT_ack_count(7),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(3)
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_2_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0000_cy(1),
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut(2),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy(2)
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_Q : MUXCY
    port map (
      CI => UUT_Mcompar_nstate_cmp_gt0000_cy(0),
      DI => N1,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut(1),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy(1)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_1_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_ack_count(2),
      I1 => UUT_ack_count(3),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(1)
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => UUT_Mcompar_nstate_cmp_gt0000_lut(0),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy(0)
    );
  UUT_Madd_ack_count_share0000_xor_11_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(10),
      LI => UUT_Madd_ack_count_share0000_xor_11_rt_180,
      O => UUT_ack_count_share0000(11)
    );
  UUT_Madd_ack_count_share0000_xor_10_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(9),
      LI => UUT_Madd_ack_count_share0000_cy_10_rt_160,
      O => UUT_ack_count_share0000(10)
    );
  UUT_Madd_ack_count_share0000_cy_10_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(9),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_10_rt_160,
      O => UUT_Madd_ack_count_share0000_cy(10)
    );
  UUT_Madd_ack_count_share0000_xor_9_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(8),
      LI => UUT_Madd_ack_count_share0000_cy_9_rt_178,
      O => UUT_ack_count_share0000(9)
    );
  UUT_Madd_ack_count_share0000_cy_9_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(8),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_9_rt_178,
      O => UUT_Madd_ack_count_share0000_cy(9)
    );
  UUT_Madd_ack_count_share0000_xor_8_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(7),
      LI => UUT_Madd_ack_count_share0000_cy_8_rt_176,
      O => UUT_ack_count_share0000(8)
    );
  UUT_Madd_ack_count_share0000_cy_8_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(7),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_8_rt_176,
      O => UUT_Madd_ack_count_share0000_cy(8)
    );
  UUT_Madd_ack_count_share0000_xor_7_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(6),
      LI => UUT_Madd_ack_count_share0000_cy_7_rt_174,
      O => UUT_ack_count_share0000(7)
    );
  UUT_Madd_ack_count_share0000_cy_7_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(6),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_7_rt_174,
      O => UUT_Madd_ack_count_share0000_cy(7)
    );
  UUT_Madd_ack_count_share0000_xor_6_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(5),
      LI => UUT_Madd_ack_count_share0000_cy_6_rt_172,
      O => UUT_ack_count_share0000(6)
    );
  UUT_Madd_ack_count_share0000_cy_6_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(5),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_6_rt_172,
      O => UUT_Madd_ack_count_share0000_cy(6)
    );
  UUT_Madd_ack_count_share0000_xor_5_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(4),
      LI => UUT_Madd_ack_count_share0000_cy_5_rt_170,
      O => UUT_ack_count_share0000(5)
    );
  UUT_Madd_ack_count_share0000_cy_5_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(4),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_5_rt_170,
      O => UUT_Madd_ack_count_share0000_cy(5)
    );
  UUT_Madd_ack_count_share0000_xor_4_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(3),
      LI => UUT_Madd_ack_count_share0000_cy_4_rt_168,
      O => UUT_ack_count_share0000(4)
    );
  UUT_Madd_ack_count_share0000_cy_4_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(3),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_4_rt_168,
      O => UUT_Madd_ack_count_share0000_cy(4)
    );
  UUT_Madd_ack_count_share0000_xor_3_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(2),
      LI => UUT_Madd_ack_count_share0000_cy_3_rt_166,
      O => UUT_ack_count_share0000(3)
    );
  UUT_Madd_ack_count_share0000_cy_3_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(2),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_3_rt_166,
      O => UUT_Madd_ack_count_share0000_cy(3)
    );
  UUT_Madd_ack_count_share0000_xor_2_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(1),
      LI => UUT_Madd_ack_count_share0000_cy_2_rt_164,
      O => UUT_ack_count_share0000(2)
    );
  UUT_Madd_ack_count_share0000_cy_2_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(1),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_2_rt_164,
      O => UUT_Madd_ack_count_share0000_cy(2)
    );
  UUT_Madd_ack_count_share0000_xor_1_Q : XORCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(0),
      LI => UUT_Madd_ack_count_share0000_cy_1_rt_162,
      O => UUT_ack_count_share0000(1)
    );
  UUT_Madd_ack_count_share0000_cy_1_Q : MUXCY
    port map (
      CI => UUT_Madd_ack_count_share0000_cy(0),
      DI => N0,
      S => UUT_Madd_ack_count_share0000_cy_1_rt_162,
      O => UUT_Madd_ack_count_share0000_cy(1)
    );
  UUT_Madd_ack_count_share0000_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => UUT_Madd_ack_count_share0000_lut(0),
      O => UUT_ack_count_share0000(0)
    );
  UUT_Madd_ack_count_share0000_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => UUT_Madd_ack_count_share0000_lut(0),
      O => UUT_Madd_ack_count_share0000_cy(0)
    );
  UUT_Madd_delay_count_share0000_xor_15_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(14),
      LI => UUT_Madd_delay_count_share0000_xor_15_rt_212,
      O => UUT_delay_count_share0000(15)
    );
  UUT_Madd_delay_count_share0000_xor_14_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(13),
      LI => UUT_Madd_delay_count_share0000_cy_14_rt_192,
      O => UUT_delay_count_share0000(14)
    );
  UUT_Madd_delay_count_share0000_cy_14_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(13),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_14_rt_192,
      O => UUT_Madd_delay_count_share0000_cy(14)
    );
  UUT_Madd_delay_count_share0000_xor_13_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(12),
      LI => UUT_Madd_delay_count_share0000_cy_13_rt_190,
      O => UUT_delay_count_share0000(13)
    );
  UUT_Madd_delay_count_share0000_cy_13_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(12),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_13_rt_190,
      O => UUT_Madd_delay_count_share0000_cy(13)
    );
  UUT_Madd_delay_count_share0000_xor_12_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(11),
      LI => UUT_Madd_delay_count_share0000_cy_12_rt_188,
      O => UUT_delay_count_share0000(12)
    );
  UUT_Madd_delay_count_share0000_cy_12_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(11),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_12_rt_188,
      O => UUT_Madd_delay_count_share0000_cy(12)
    );
  UUT_Madd_delay_count_share0000_xor_11_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(10),
      LI => UUT_Madd_delay_count_share0000_cy_11_rt_186,
      O => UUT_delay_count_share0000(11)
    );
  UUT_Madd_delay_count_share0000_cy_11_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(10),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_11_rt_186,
      O => UUT_Madd_delay_count_share0000_cy(11)
    );
  UUT_Madd_delay_count_share0000_xor_10_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(9),
      LI => UUT_Madd_delay_count_share0000_cy_10_rt_184,
      O => UUT_delay_count_share0000(10)
    );
  UUT_Madd_delay_count_share0000_cy_10_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(9),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_10_rt_184,
      O => UUT_Madd_delay_count_share0000_cy(10)
    );
  UUT_Madd_delay_count_share0000_xor_9_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(8),
      LI => UUT_Madd_delay_count_share0000_cy_9_rt_210,
      O => UUT_delay_count_share0000(9)
    );
  UUT_Madd_delay_count_share0000_cy_9_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(8),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_9_rt_210,
      O => UUT_Madd_delay_count_share0000_cy(9)
    );
  UUT_Madd_delay_count_share0000_xor_8_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(7),
      LI => UUT_Madd_delay_count_share0000_cy_8_rt_208,
      O => UUT_delay_count_share0000(8)
    );
  UUT_Madd_delay_count_share0000_cy_8_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(7),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_8_rt_208,
      O => UUT_Madd_delay_count_share0000_cy(8)
    );
  UUT_Madd_delay_count_share0000_xor_7_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(6),
      LI => UUT_Madd_delay_count_share0000_cy_7_rt_206,
      O => UUT_delay_count_share0000(7)
    );
  UUT_Madd_delay_count_share0000_cy_7_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(6),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_7_rt_206,
      O => UUT_Madd_delay_count_share0000_cy(7)
    );
  UUT_Madd_delay_count_share0000_xor_6_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(5),
      LI => UUT_Madd_delay_count_share0000_cy_6_rt_204,
      O => UUT_delay_count_share0000(6)
    );
  UUT_Madd_delay_count_share0000_cy_6_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(5),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_6_rt_204,
      O => UUT_Madd_delay_count_share0000_cy(6)
    );
  UUT_Madd_delay_count_share0000_xor_5_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(4),
      LI => UUT_Madd_delay_count_share0000_cy_5_rt_202,
      O => UUT_delay_count_share0000(5)
    );
  UUT_Madd_delay_count_share0000_cy_5_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(4),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_5_rt_202,
      O => UUT_Madd_delay_count_share0000_cy(5)
    );
  UUT_Madd_delay_count_share0000_xor_4_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(3),
      LI => UUT_Madd_delay_count_share0000_cy_4_rt_200,
      O => UUT_delay_count_share0000(4)
    );
  UUT_Madd_delay_count_share0000_cy_4_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(3),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_4_rt_200,
      O => UUT_Madd_delay_count_share0000_cy(4)
    );
  UUT_Madd_delay_count_share0000_xor_3_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(2),
      LI => UUT_Madd_delay_count_share0000_cy_3_rt_198,
      O => UUT_delay_count_share0000(3)
    );
  UUT_Madd_delay_count_share0000_cy_3_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(2),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_3_rt_198,
      O => UUT_Madd_delay_count_share0000_cy(3)
    );
  UUT_Madd_delay_count_share0000_xor_2_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(1),
      LI => UUT_Madd_delay_count_share0000_cy_2_rt_196,
      O => UUT_delay_count_share0000(2)
    );
  UUT_Madd_delay_count_share0000_cy_2_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(1),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_2_rt_196,
      O => UUT_Madd_delay_count_share0000_cy(2)
    );
  UUT_Madd_delay_count_share0000_xor_1_Q : XORCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(0),
      LI => UUT_Madd_delay_count_share0000_cy_1_rt_194,
      O => UUT_delay_count_share0000(1)
    );
  UUT_Madd_delay_count_share0000_cy_1_Q : MUXCY
    port map (
      CI => UUT_Madd_delay_count_share0000_cy(0),
      DI => N0,
      S => UUT_Madd_delay_count_share0000_cy_1_rt_194,
      O => UUT_Madd_delay_count_share0000_cy(1)
    );
  UUT_Madd_delay_count_share0000_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => UUT_Madd_delay_count_share0000_lut(0),
      O => UUT_delay_count_share0000(0)
    );
  UUT_Madd_delay_count_share0000_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => UUT_Madd_delay_count_share0000_lut(0),
      O => UUT_Madd_delay_count_share0000_cy(0)
    );
  UUT_Madd_writeCount_share0000_xor_30_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(29),
      LI => UUT_Madd_writeCount_share0000_xor_30_rt_273,
      O => UUT_writeCount_share0000(30)
    );
  UUT_Madd_writeCount_share0000_xor_29_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(28),
      LI => UUT_Madd_writeCount_share0000_cy_29_rt_255,
      O => UUT_writeCount_share0000(29)
    );
  UUT_Madd_writeCount_share0000_cy_29_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(28),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_29_rt_255,
      O => UUT_Madd_writeCount_share0000_cy(29)
    );
  UUT_Madd_writeCount_share0000_xor_28_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(27),
      LI => UUT_Madd_writeCount_share0000_cy_28_rt_253,
      O => UUT_writeCount_share0000(28)
    );
  UUT_Madd_writeCount_share0000_cy_28_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(27),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_28_rt_253,
      O => UUT_Madd_writeCount_share0000_cy(28)
    );
  UUT_Madd_writeCount_share0000_xor_27_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(26),
      LI => UUT_Madd_writeCount_share0000_cy_27_rt_251,
      O => UUT_writeCount_share0000(27)
    );
  UUT_Madd_writeCount_share0000_cy_27_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(26),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_27_rt_251,
      O => UUT_Madd_writeCount_share0000_cy(27)
    );
  UUT_Madd_writeCount_share0000_xor_26_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(25),
      LI => UUT_Madd_writeCount_share0000_cy_26_rt_249,
      O => UUT_writeCount_share0000(26)
    );
  UUT_Madd_writeCount_share0000_cy_26_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(25),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_26_rt_249,
      O => UUT_Madd_writeCount_share0000_cy(26)
    );
  UUT_Madd_writeCount_share0000_xor_25_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(24),
      LI => UUT_Madd_writeCount_share0000_cy_25_rt_247,
      O => UUT_writeCount_share0000(25)
    );
  UUT_Madd_writeCount_share0000_cy_25_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(24),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_25_rt_247,
      O => UUT_Madd_writeCount_share0000_cy(25)
    );
  UUT_Madd_writeCount_share0000_xor_24_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(23),
      LI => UUT_Madd_writeCount_share0000_cy_24_rt_245,
      O => UUT_writeCount_share0000(24)
    );
  UUT_Madd_writeCount_share0000_cy_24_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(23),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_24_rt_245,
      O => UUT_Madd_writeCount_share0000_cy(24)
    );
  UUT_Madd_writeCount_share0000_xor_23_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(22),
      LI => UUT_Madd_writeCount_share0000_cy_23_rt_243,
      O => UUT_writeCount_share0000(23)
    );
  UUT_Madd_writeCount_share0000_cy_23_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(22),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_23_rt_243,
      O => UUT_Madd_writeCount_share0000_cy(23)
    );
  UUT_Madd_writeCount_share0000_xor_22_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(21),
      LI => UUT_Madd_writeCount_share0000_cy_22_rt_241,
      O => UUT_writeCount_share0000(22)
    );
  UUT_Madd_writeCount_share0000_cy_22_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(21),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_22_rt_241,
      O => UUT_Madd_writeCount_share0000_cy(22)
    );
  UUT_Madd_writeCount_share0000_xor_21_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(20),
      LI => UUT_Madd_writeCount_share0000_cy_21_rt_239,
      O => UUT_writeCount_share0000(21)
    );
  UUT_Madd_writeCount_share0000_cy_21_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(20),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_21_rt_239,
      O => UUT_Madd_writeCount_share0000_cy(21)
    );
  UUT_Madd_writeCount_share0000_xor_20_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(19),
      LI => UUT_Madd_writeCount_share0000_cy_20_rt_237,
      O => UUT_writeCount_share0000(20)
    );
  UUT_Madd_writeCount_share0000_cy_20_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(19),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_20_rt_237,
      O => UUT_Madd_writeCount_share0000_cy(20)
    );
  UUT_Madd_writeCount_share0000_xor_19_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(18),
      LI => UUT_Madd_writeCount_share0000_cy_19_rt_233,
      O => UUT_writeCount_share0000(19)
    );
  UUT_Madd_writeCount_share0000_cy_19_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(18),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_19_rt_233,
      O => UUT_Madd_writeCount_share0000_cy(19)
    );
  UUT_Madd_writeCount_share0000_xor_18_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(17),
      LI => UUT_Madd_writeCount_share0000_cy_18_rt_231,
      O => UUT_writeCount_share0000(18)
    );
  UUT_Madd_writeCount_share0000_cy_18_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(17),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_18_rt_231,
      O => UUT_Madd_writeCount_share0000_cy(18)
    );
  UUT_Madd_writeCount_share0000_xor_17_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(16),
      LI => UUT_Madd_writeCount_share0000_cy_17_rt_229,
      O => UUT_writeCount_share0000(17)
    );
  UUT_Madd_writeCount_share0000_cy_17_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(16),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_17_rt_229,
      O => UUT_Madd_writeCount_share0000_cy(17)
    );
  UUT_Madd_writeCount_share0000_xor_16_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(15),
      LI => UUT_Madd_writeCount_share0000_cy_16_rt_227,
      O => UUT_writeCount_share0000(16)
    );
  UUT_Madd_writeCount_share0000_cy_16_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(15),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_16_rt_227,
      O => UUT_Madd_writeCount_share0000_cy(16)
    );
  UUT_Madd_writeCount_share0000_xor_15_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(14),
      LI => UUT_Madd_writeCount_share0000_cy_15_rt_225,
      O => UUT_writeCount_share0000(15)
    );
  UUT_Madd_writeCount_share0000_cy_15_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(14),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_15_rt_225,
      O => UUT_Madd_writeCount_share0000_cy(15)
    );
  UUT_Madd_writeCount_share0000_xor_14_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(13),
      LI => UUT_Madd_writeCount_share0000_cy_14_rt_223,
      O => UUT_writeCount_share0000(14)
    );
  UUT_Madd_writeCount_share0000_cy_14_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(13),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_14_rt_223,
      O => UUT_Madd_writeCount_share0000_cy(14)
    );
  UUT_Madd_writeCount_share0000_xor_13_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(12),
      LI => UUT_Madd_writeCount_share0000_cy_13_rt_221,
      O => UUT_writeCount_share0000(13)
    );
  UUT_Madd_writeCount_share0000_cy_13_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(12),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_13_rt_221,
      O => UUT_Madd_writeCount_share0000_cy(13)
    );
  UUT_Madd_writeCount_share0000_xor_12_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(11),
      LI => UUT_Madd_writeCount_share0000_cy_12_rt_219,
      O => UUT_writeCount_share0000(12)
    );
  UUT_Madd_writeCount_share0000_cy_12_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(11),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_12_rt_219,
      O => UUT_Madd_writeCount_share0000_cy(12)
    );
  UUT_Madd_writeCount_share0000_xor_11_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(10),
      LI => UUT_Madd_writeCount_share0000_cy_11_rt_217,
      O => UUT_writeCount_share0000(11)
    );
  UUT_Madd_writeCount_share0000_cy_11_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(10),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_11_rt_217,
      O => UUT_Madd_writeCount_share0000_cy(11)
    );
  UUT_Madd_writeCount_share0000_xor_10_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(9),
      LI => UUT_Madd_writeCount_share0000_cy_10_rt_215,
      O => UUT_writeCount_share0000(10)
    );
  UUT_Madd_writeCount_share0000_cy_10_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(9),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_10_rt_215,
      O => UUT_Madd_writeCount_share0000_cy(10)
    );
  UUT_Madd_writeCount_share0000_xor_9_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(8),
      LI => UUT_Madd_writeCount_share0000_cy_9_rt_271,
      O => UUT_writeCount_share0000(9)
    );
  UUT_Madd_writeCount_share0000_cy_9_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(8),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_9_rt_271,
      O => UUT_Madd_writeCount_share0000_cy(9)
    );
  UUT_Madd_writeCount_share0000_xor_8_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(7),
      LI => UUT_Madd_writeCount_share0000_cy_8_rt_269,
      O => UUT_writeCount_share0000(8)
    );
  UUT_Madd_writeCount_share0000_cy_8_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(7),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_8_rt_269,
      O => UUT_Madd_writeCount_share0000_cy(8)
    );
  UUT_Madd_writeCount_share0000_xor_7_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(6),
      LI => UUT_Madd_writeCount_share0000_cy_7_rt_267,
      O => UUT_writeCount_share0000(7)
    );
  UUT_Madd_writeCount_share0000_cy_7_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(6),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_7_rt_267,
      O => UUT_Madd_writeCount_share0000_cy(7)
    );
  UUT_Madd_writeCount_share0000_xor_6_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(5),
      LI => UUT_Madd_writeCount_share0000_cy_6_rt_265,
      O => UUT_writeCount_share0000(6)
    );
  UUT_Madd_writeCount_share0000_cy_6_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(5),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_6_rt_265,
      O => UUT_Madd_writeCount_share0000_cy(6)
    );
  UUT_Madd_writeCount_share0000_xor_5_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(4),
      LI => UUT_Madd_writeCount_share0000_cy_5_rt_263,
      O => UUT_writeCount_share0000(5)
    );
  UUT_Madd_writeCount_share0000_cy_5_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(4),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_5_rt_263,
      O => UUT_Madd_writeCount_share0000_cy(5)
    );
  UUT_Madd_writeCount_share0000_xor_4_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(3),
      LI => UUT_Madd_writeCount_share0000_cy_4_rt_261,
      O => UUT_writeCount_share0000(4)
    );
  UUT_Madd_writeCount_share0000_cy_4_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(3),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_4_rt_261,
      O => UUT_Madd_writeCount_share0000_cy(4)
    );
  UUT_Madd_writeCount_share0000_xor_3_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(2),
      LI => UUT_Madd_writeCount_share0000_cy_3_rt_259,
      O => UUT_writeCount_share0000(3)
    );
  UUT_Madd_writeCount_share0000_cy_3_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(2),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_3_rt_259,
      O => UUT_Madd_writeCount_share0000_cy(3)
    );
  UUT_Madd_writeCount_share0000_xor_2_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(1),
      LI => UUT_Madd_writeCount_share0000_cy_2_rt_257,
      O => UUT_writeCount_share0000(2)
    );
  UUT_Madd_writeCount_share0000_cy_2_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(1),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_2_rt_257,
      O => UUT_Madd_writeCount_share0000_cy(2)
    );
  UUT_Madd_writeCount_share0000_xor_1_Q : XORCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(0),
      LI => UUT_Madd_writeCount_share0000_cy_1_rt_235,
      O => UUT_writeCount_share0000(1)
    );
  UUT_Madd_writeCount_share0000_cy_1_Q : MUXCY
    port map (
      CI => UUT_Madd_writeCount_share0000_cy(0),
      DI => N0,
      S => UUT_Madd_writeCount_share0000_cy_1_rt_235,
      O => UUT_Madd_writeCount_share0000_cy(1)
    );
  UUT_Madd_writeCount_share0000_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => UUT_Madd_writeCount_share0000_lut(0),
      O => UUT_writeCount_share0000(0)
    );
  UUT_Madd_writeCount_share0000_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => UUT_Madd_writeCount_share0000_lut(0),
      O => UUT_Madd_writeCount_share0000_cy(0)
    );
  UUT_nstate_FFd3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_nstate_FFd3_In_514,
      Q => UUT_nstate_FFd3_513
    );
  UUT_Mtrien_in_i2c : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      CE => UUT_Mtridata_in_i2c_not0001,
      D => UUT_Mtrien_in_i2c_mux0000,
      Q => UUT_Mtrien_in_i2c_353
    );
  UUT_ack_count_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(11),
      Q => UUT_ack_count(11)
    );
  UUT_ack_count_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(10),
      Q => UUT_ack_count(10)
    );
  UUT_ack_count_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(9),
      Q => UUT_ack_count(9)
    );
  UUT_ack_count_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(8),
      Q => UUT_ack_count(8)
    );
  UUT_ack_count_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(7),
      Q => UUT_ack_count(7)
    );
  UUT_ack_count_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(6),
      Q => UUT_ack_count(6)
    );
  UUT_ack_count_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(5),
      Q => UUT_ack_count(5)
    );
  UUT_ack_count_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(4),
      Q => UUT_ack_count(4)
    );
  UUT_ack_count_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(3),
      Q => UUT_ack_count(3)
    );
  UUT_ack_count_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(2),
      Q => UUT_ack_count(2)
    );
  UUT_ack_count_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000(1),
      Q => UUT_ack_count(1)
    );
  UUT_writeCount_30 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(30),
      Q => UUT_writeCount(30)
    );
  UUT_writeCount_29 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(29),
      Q => UUT_writeCount(29)
    );
  UUT_writeCount_28 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(28),
      Q => UUT_writeCount(28)
    );
  UUT_writeCount_27 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(27),
      Q => UUT_writeCount(27)
    );
  UUT_writeCount_26 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(26),
      Q => UUT_writeCount(26)
    );
  UUT_writeCount_25 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(25),
      Q => UUT_writeCount(25)
    );
  UUT_writeCount_24 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(24),
      Q => UUT_writeCount(24)
    );
  UUT_writeCount_23 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(23),
      Q => UUT_writeCount(23)
    );
  UUT_writeCount_22 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(22),
      Q => UUT_writeCount(22)
    );
  UUT_writeCount_21 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(21),
      Q => UUT_writeCount(21)
    );
  UUT_writeCount_20 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(20),
      Q => UUT_writeCount(20)
    );
  UUT_writeCount_19 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(19),
      Q => UUT_writeCount(19)
    );
  UUT_writeCount_18 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(18),
      Q => UUT_writeCount(18)
    );
  UUT_writeCount_17 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(17),
      Q => UUT_writeCount(17)
    );
  UUT_writeCount_16 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(16),
      Q => UUT_writeCount(16)
    );
  UUT_writeCount_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(15),
      Q => UUT_writeCount(15)
    );
  UUT_writeCount_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(14),
      Q => UUT_writeCount(14)
    );
  UUT_writeCount_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(13),
      Q => UUT_writeCount(13)
    );
  UUT_writeCount_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(12),
      Q => UUT_writeCount(12)
    );
  UUT_writeCount_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(11),
      Q => UUT_writeCount(11)
    );
  UUT_writeCount_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(10),
      Q => UUT_writeCount(10)
    );
  UUT_writeCount_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(9),
      Q => UUT_writeCount(9)
    );
  UUT_writeCount_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(8),
      Q => UUT_writeCount(8)
    );
  UUT_writeCount_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(7),
      Q => UUT_writeCount(7)
    );
  UUT_writeCount_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(6),
      Q => UUT_writeCount(6)
    );
  UUT_writeCount_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(5),
      Q => UUT_writeCount(5)
    );
  UUT_writeCount_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(4),
      Q => UUT_writeCount(4)
    );
  UUT_writeCount_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(3),
      Q => UUT_writeCount(3)
    );
  UUT_writeCount_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(2),
      Q => UUT_writeCount(2)
    );
  UUT_writeCount_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(1),
      Q => UUT_writeCount(1)
    );
  UUT_writeCount_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_writeCount_mux0000(0),
      Q => UUT_writeCount(0)
    );
  UUT_counter_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_counter_mux0000(0),
      Q => UUT_counter(4)
    );
  UUT_counter_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_counter_mux0000(1),
      Q => UUT_counter(3)
    );
  UUT_counter_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_counter_mux0000(2),
      Q => UUT_counter(2)
    );
  UUT_counter_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_counter_mux0000(3),
      Q => UUT_counter(1)
    );
  UUT_prevClk : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_prevClk_mux0000,
      Q => UUT_prevClk_545
    );
  UUT_Mtridata_in_i2c : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      CE => UUT_Mtridata_in_i2c_not0001,
      D => UUT_Mtridata_in_i2c_mux0000,
      Q => UUT_Mtridata_in_i2c_334
    );
  UUT_delay_count_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(15),
      Q => UUT_delay_count(15)
    );
  UUT_delay_count_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(14),
      Q => UUT_delay_count(14)
    );
  UUT_delay_count_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(13),
      Q => UUT_delay_count(13)
    );
  UUT_delay_count_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(12),
      Q => UUT_delay_count(12)
    );
  UUT_delay_count_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(11),
      Q => UUT_delay_count(11)
    );
  UUT_delay_count_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(10),
      Q => UUT_delay_count(10)
    );
  UUT_delay_count_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(9),
      Q => UUT_delay_count(9)
    );
  UUT_delay_count_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(8),
      Q => UUT_delay_count(8)
    );
  UUT_delay_count_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(7),
      Q => UUT_delay_count(7)
    );
  UUT_delay_count_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(6),
      Q => UUT_delay_count(6)
    );
  UUT_delay_count_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(5),
      Q => UUT_delay_count(5)
    );
  UUT_delay_count_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(4),
      Q => UUT_delay_count(4)
    );
  UUT_delay_count_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(3),
      Q => UUT_delay_count(3)
    );
  UUT_delay_count_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(2),
      Q => UUT_delay_count(2)
    );
  UUT_delay_count_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000(1),
      Q => UUT_delay_count(1)
    );
  UUT_ClkEdge_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ClkEdge(0),
      Q => UUT_ClkEdge(1)
    );
  UUT_ClkEdge_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => CLK_sI2C_Clk_23,
      Q => UUT_ClkEdge(0)
    );
  UUT_pstate_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_pstate_mux0000(5),
      Q => UUT_pstate(3)
    );
  UUT_pstate_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_pstate_mux0000(6),
      Q => UUT_pstate(2)
    );
  UUT_ClkFallingEdge : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => N1,
      R => UUT_ClkFallingEdge_not0001,
      Q => UUT_ClkFallingEdge_145
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_0_Q : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_writeCount(8),
      I1 => UUT_writeCount(7),
      I2 => UUT_writeCount(9),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(0)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(0),
      O => UUT_shiftReg_cmp_eq0001_wg_cy(0)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_1_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_writeCount(10),
      I1 => UUT_writeCount(11),
      I2 => UUT_writeCount(6),
      I3 => UUT_writeCount(12),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(1)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_Q : MUXCY
    port map (
      CI => UUT_shiftReg_cmp_eq0001_wg_cy(0),
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(1),
      O => UUT_shiftReg_cmp_eq0001_wg_cy(1)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_2_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_writeCount(13),
      I1 => UUT_writeCount(14),
      I2 => UUT_writeCount(5),
      I3 => UUT_writeCount(15),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(2)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_2_Q : MUXCY
    port map (
      CI => UUT_shiftReg_cmp_eq0001_wg_cy(1),
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(2),
      O => UUT_shiftReg_cmp_eq0001_wg_cy(2)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_3_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_writeCount(16),
      I1 => UUT_writeCount(17),
      I2 => UUT_writeCount(4),
      I3 => UUT_writeCount(18),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(3)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_Q : MUXCY
    port map (
      CI => UUT_shiftReg_cmp_eq0001_wg_cy(2),
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(3),
      O => UUT_shiftReg_cmp_eq0001_wg_cy(3)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_4_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_writeCount(19),
      I1 => UUT_writeCount(20),
      I2 => UUT_writeCount(3),
      I3 => UUT_writeCount(21),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(4)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_4_Q : MUXCY
    port map (
      CI => UUT_shiftReg_cmp_eq0001_wg_cy(3),
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(4),
      O => UUT_shiftReg_cmp_eq0001_wg_cy(4)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_5_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_writeCount(22),
      I1 => UUT_writeCount(23),
      I2 => UUT_writeCount(2),
      I3 => UUT_writeCount(24),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(5)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_Q : MUXCY
    port map (
      CI => UUT_shiftReg_cmp_eq0001_wg_cy(4),
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(5),
      O => UUT_shiftReg_cmp_eq0001_wg_cy(5)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_6_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_writeCount(25),
      I1 => UUT_writeCount(26),
      I2 => UUT_writeCount(1),
      I3 => UUT_writeCount(27),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(6)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_6_Q : MUXCY
    port map (
      CI => UUT_shiftReg_cmp_eq0001_wg_cy(5),
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(6),
      O => UUT_shiftReg_cmp_eq0001_wg_cy(6)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_7_Q : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_writeCount(30),
      I1 => UUT_writeCount(28),
      I2 => UUT_writeCount(0),
      I3 => UUT_writeCount(29),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(7)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_7_Q : MUXCY
    port map (
      CI => UUT_shiftReg_cmp_eq0001_wg_cy(6),
      DI => N0,
      S => UUT_shiftReg_cmp_eq0001_wg_lut(7),
      O => UUT_shiftReg_cmp_eq0001
    );
  UUT_prevClk_mux00001 : LUT3
    generic map(
      INIT => X"E8"
    )
    port map (
      I0 => UUT_ClkEdge(1),
      I1 => UUT_prevClk_545,
      I2 => UUT_ClkEdge(0),
      O => UUT_prevClk_mux0000
    );
  UUT_ClkFallingEdge_not00011 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => UUT_ClkEdge(0),
      I1 => UUT_prevClk_545,
      I2 => UUT_ClkEdge(1),
      O => UUT_ClkFallingEdge_not0001
    );
  CLK_sI2C_Clk_cmp_eq00007 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => CLK_clk_div(5),
      I1 => CLK_clk_div(4),
      I2 => CLK_clk_div(6),
      I3 => CLK_clk_div(7),
      O => CLK_sI2C_Clk_cmp_eq00007_26
    );
  CLK_sI2C_Clk_cmp_eq000016 : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => CLK_clk_div(3),
      I1 => CLK_clk_div(2),
      I2 => CLK_clk_div(1),
      I3 => CLK_clk_div(0),
      O => CLK_sI2C_Clk_cmp_eq000016_25
    );
  CLK_sI2C_Clk_cmp_eq000017 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => CLK_sI2C_Clk_cmp_eq00007_26,
      I1 => CLK_sI2C_Clk_cmp_eq000016_25,
      O => CLK_sI2C_Clk_cmp_eq0000
    );
  UUT_counter_mux0000_4_1 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_nstate_FFd1_509,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd3_513,
      I3 => N01,
      O => UUT_N121
    );
  UUT_counter_mux0000_4_111 : LUT4
    generic map(
      INIT => X"EC20"
    )
    port map (
      I0 => UUT_ClkRisingEdge_147,
      I1 => UUT_counter(0),
      I2 => UUT_nstate_cmp_eq0010,
      I3 => UUT_N121,
      O => UUT_counter_mux0000_4_11
    );
  UUT_Madd_counter_addsub0000_cy_2_11 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => UUT_counter(0),
      I1 => UUT_counter(1),
      I2 => UUT_counter(2),
      O => UUT_Madd_counter_addsub0000_cy(2)
    );
  UUT_N641 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_ClkRisingEdge_147,
      I1 => UUT_nstate_cmp_eq0010,
      O => UUT_N64
    );
  UUT_nstate_FFd3_In_SW1 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_pstate(3),
      I3 => UUT_pstate(2),
      O => N13
    );
  UUT_in_i2cLogicTrst1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => UUT_Mtridata_in_i2c_334,
      I1 => UUT_Mtrien_in_i2c_353,
      O => UUT_in_i2c
    );
  UUT_out_i2cclk_mux0000331 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_ack_count(3),
      I1 => UUT_ack_count(0),
      I2 => UUT_ack_count(6),
      O => UUT_N67
    );
  UUT_Dir_mux0000143 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(7),
      I2 => UUT_delay_count(6),
      I3 => UUT_delay_count(4),
      O => UUT_Dir_mux0000143_152
    );
  UUT_Dir_mux0000148 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_delay_count(2),
      I1 => UUT_delay_count(1),
      I2 => UUT_delay_count(10),
      I3 => UUT_delay_count(0),
      O => UUT_Dir_mux0000148_153
    );
  UUT_out_i2cclk_mux0000621 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd4_515,
      O => UUT_N60
    );
  UUT_Dir_mux0000432 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd3_513,
      O => UUT_N72
    );
  UUT_nstate_Out31 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_nstate_FFd4_515,
      O => UUT_nstate_cmp_eq0008
    );
  UUT_delay_count_mux0000_0_18 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => UUT_delay_count_and0000,
      I1 => UUT_delay_count_or0001,
      I2 => UUT_delay_count_mux0000_0_6_474,
      I3 => UUT_delay_count_mux0000_0_0_467,
      O => UUT_delay_count_mux0000_0_18_471
    );
  UUT_delay_count_mux0000_9_1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => N177,
      I2 => UUT_delay_count_share0000(9),
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(9)
    );
  UUT_delay_count_mux0000_8_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(8),
      I1 => UUT_delay_count_share0000(8),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(8)
    );
  UUT_delay_count_mux0000_7_1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => UUT_delay_count(7),
      I1 => UUT_delay_count_or0000,
      I2 => UUT_delay_count_share0000(7),
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(7)
    );
  UUT_delay_count_mux0000_6_1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => UUT_delay_count(6),
      I1 => UUT_delay_count_or0000,
      I2 => UUT_delay_count_share0000(6),
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(6)
    );
  UUT_delay_count_mux0000_5_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(5),
      I1 => UUT_delay_count_share0000(5),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(5)
    );
  UUT_delay_count_mux0000_4_1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => UUT_delay_count(4),
      I1 => UUT_delay_count_or0000,
      I2 => UUT_delay_count_share0000(4),
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(4)
    );
  UUT_delay_count_mux0000_3_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(3),
      I1 => UUT_delay_count_share0000(3),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(3)
    );
  UUT_delay_count_mux0000_2_1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => UUT_delay_count(2),
      I1 => UUT_delay_count_or0000,
      I2 => UUT_delay_count_share0000(2),
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(2)
    );
  UUT_delay_count_mux0000_1_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(1),
      I1 => UUT_delay_count_share0000(1),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(1)
    );
  UUT_delay_count_mux0000_15_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(15),
      I1 => UUT_delay_count_share0000(15),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(15)
    );
  UUT_delay_count_mux0000_14_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(14),
      I1 => UUT_delay_count_share0000(14),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(14)
    );
  UUT_delay_count_mux0000_13_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(13),
      I1 => UUT_delay_count_share0000(13),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(13)
    );
  UUT_delay_count_mux0000_12_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(12),
      I1 => UUT_delay_count_share0000(12),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(12)
    );
  UUT_delay_count_mux0000_11_2 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_delay_count(11),
      I1 => UUT_delay_count_share0000(11),
      I2 => UUT_N15,
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(11)
    );
  UUT_delay_count_mux0000_10_1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => UUT_delay_count(10),
      I1 => UUT_delay_count_or0000,
      I2 => UUT_delay_count_share0000(10),
      I3 => UUT_N4,
      O => UUT_delay_count_mux0000(10)
    );
  UUT_delay_count_mux0000_0_117 : LUT4
    generic map(
      INIT => X"A2AA"
    )
    port map (
      I0 => UUT_delay_count(10),
      I1 => UUT_delay_count(4),
      I2 => UUT_delay_count_mux0000_0_181_472,
      I3 => UUT_delay_count(2),
      O => UUT_delay_count_mux0000_0_117_468
    );
  UUT_delay_count_mux0000_0_122 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(2),
      I1 => UUT_delay_count(10),
      O => UUT_delay_count_mux0000_0_122_469
    );
  UUT_nstate_FFd4_In0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0000_520,
      I1 => UUT_nstate_cmp_eq0010,
      O => UUT_nstate_FFd4_In0_516
    );
  UUT_writeCount_mux0000_0_SW1 : LUT4
    generic map(
      INIT => X"F8B8"
    )
    port map (
      I0 => UUT_writeCount_share0000(0),
      I1 => UUT_ClkFallingEdge_145,
      I2 => UUT_writeCount(0),
      I3 => UUT_delay_count_or0000,
      O => N21
    );
  UUT_writeCount_mux0000_0_Q : LUT4
    generic map(
      INIT => X"EE4E"
    )
    port map (
      I0 => UUT_delay_count_or0001,
      I1 => N20,
      I2 => UUT_N13,
      I3 => N21,
      O => UUT_writeCount_mux0000(0)
    );
  UUT_Dir_mux00012 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_delay_count(6),
      I1 => UUT_delay_count(4),
      I2 => UUT_delay_count(7),
      I3 => N23,
      O => UUT_shiftReg_cmp_eq0002
    );
  UUT_ack_count_or000421 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => UUT_ack_count(4),
      I1 => UUT_ack_count(3),
      I2 => UUT_ack_count(0),
      O => UUT_N351
    );
  UUT_ack_count_mux0000_6_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count_share0000(6),
      I2 => N179,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(6)
    );
  UUT_ack_count_mux0000_5_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count_share0000(5),
      I2 => UUT_N211,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(5)
    );
  UUT_ack_count_mux0000_4_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(4),
      I1 => UUT_ack_count_share0000(4),
      I2 => UUT_N211,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(4)
    );
  UUT_ack_count_mux0000_3_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(3),
      I1 => UUT_ack_count_share0000(3),
      I2 => UUT_N211,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(3)
    );
  UUT_nstate_cmp_eq0000 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_counter(0),
      I1 => UUT_counter(1),
      I2 => UUT_counter(4),
      I3 => N25,
      O => UUT_nstate_cmp_eq0000_520
    );
  UUT_Mtridata_in_i2c_mux000031 : LUT4
    generic map(
      INIT => X"0103"
    )
    port map (
      I0 => UUT_N70,
      I1 => UUT_nstate_cmp_eq0008,
      I2 => UUT_N60,
      I3 => N27,
      O => UUT_N55
    );
  UUT_N33 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => UUT_ack_count(3),
      I1 => UUT_ack_count(0),
      O => UUT_N332
    );
  UUT_N349 : LUT4
    generic map(
      INIT => X"A8AA"
    )
    port map (
      I0 => UUT_nstate_FFd1_509,
      I1 => UUT_N327_375,
      I2 => UUT_N320_374,
      I3 => UUT_ack_count_and0025,
      O => UUT_N349_379
    );
  UUT_N3178 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => UUT_N392_384,
      I1 => UUT_ack_count(8),
      I2 => UUT_N3157_371,
      I3 => UUT_N3106_370,
      O => UUT_N3178_372
    );
  UUT_N3205 : LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0011,
      I1 => UUT_N3178_372,
      I2 => UUT_N362_382,
      I3 => UUT_N349_379,
      O => UUT_N3
    );
  UUT_out_i2cclk_mux000055 : LUT4
    generic map(
      INIT => X"FAF8"
    )
    port map (
      I0 => UUT_ack_count_and0025,
      I1 => UUT_out_i2cclk_mux00002,
      I2 => UUT_nstate_cmp_eq0005,
      I3 => UUT_out_i2cclk_mux000020_535,
      O => UUT_out_i2cclk_mux000055_542
    );
  UUT_out_i2cclk_mux000071 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => N184,
      I1 => UUT_ack_count(1),
      I2 => UUT_ack_count(5),
      I3 => UUT_ack_count(8),
      O => UUT_out_i2cclk_mux000071_543
    );
  UUT_out_i2cclk_mux000083 : LUT4
    generic map(
      INIT => X"FF57"
    )
    port map (
      I0 => UUT_ack_count(4),
      I1 => UUT_ack_count(5),
      I2 => UUT_ack_count(7),
      I3 => UUT_ack_count(0),
      O => UUT_out_i2cclk_mux000083_544
    );
  UUT_out_i2cclk_mux0000142 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd2_511,
      O => UUT_out_i2cclk_mux0000142_530
    );
  UUT_writeCount_mux0000_9_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(9),
      I1 => UUT_writeCount_share0000(9),
      I2 => N193,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(9)
    );
  UUT_writeCount_mux0000_8_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(8),
      I1 => UUT_writeCount_share0000(8),
      I2 => UUT_N35,
      I3 => N181,
      O => UUT_writeCount_mux0000(8)
    );
  UUT_writeCount_mux0000_7_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(7),
      I1 => UUT_writeCount_share0000(7),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(7)
    );
  UUT_writeCount_mux0000_6_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(6),
      I1 => UUT_writeCount_share0000(6),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(6)
    );
  UUT_writeCount_mux0000_5_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(5),
      I1 => UUT_writeCount_share0000(5),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(5)
    );
  UUT_writeCount_mux0000_4_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(4),
      I1 => UUT_writeCount_share0000(4),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(4)
    );
  UUT_writeCount_mux0000_3_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(3),
      I1 => UUT_writeCount_share0000(3),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(3)
    );
  UUT_writeCount_mux0000_30_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(30),
      I1 => UUT_writeCount_share0000(30),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(30)
    );
  UUT_writeCount_mux0000_2_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(2),
      I1 => UUT_writeCount_share0000(2),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(2)
    );
  UUT_writeCount_mux0000_29_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(29),
      I1 => UUT_writeCount_share0000(29),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(29)
    );
  UUT_writeCount_mux0000_28_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(28),
      I1 => UUT_writeCount_share0000(28),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(28)
    );
  UUT_writeCount_mux0000_27_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(27),
      I1 => UUT_writeCount_share0000(27),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(27)
    );
  UUT_writeCount_mux0000_26_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(26),
      I1 => UUT_writeCount_share0000(26),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(26)
    );
  UUT_writeCount_mux0000_25_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(25),
      I1 => UUT_writeCount_share0000(25),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(25)
    );
  UUT_writeCount_mux0000_24_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(24),
      I1 => UUT_writeCount_share0000(24),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(24)
    );
  UUT_writeCount_mux0000_23_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(23),
      I1 => UUT_writeCount_share0000(23),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(23)
    );
  UUT_writeCount_mux0000_22_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(22),
      I1 => UUT_writeCount_share0000(22),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(22)
    );
  UUT_writeCount_mux0000_21_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(21),
      I1 => UUT_writeCount_share0000(21),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(21)
    );
  UUT_writeCount_mux0000_20_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(20),
      I1 => UUT_writeCount_share0000(20),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(20)
    );
  UUT_writeCount_mux0000_1_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(1),
      I1 => UUT_writeCount_share0000(1),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(1)
    );
  UUT_writeCount_mux0000_19_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(19),
      I1 => UUT_writeCount_share0000(19),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(19)
    );
  UUT_writeCount_mux0000_18_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(18),
      I1 => UUT_writeCount_share0000(18),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(18)
    );
  UUT_writeCount_mux0000_17_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(17),
      I1 => UUT_writeCount_share0000(17),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(17)
    );
  UUT_writeCount_mux0000_16_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(16),
      I1 => UUT_writeCount_share0000(16),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(16)
    );
  UUT_writeCount_mux0000_15_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(15),
      I1 => UUT_writeCount_share0000(15),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(15)
    );
  UUT_writeCount_mux0000_14_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(14),
      I1 => UUT_writeCount_share0000(14),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(14)
    );
  UUT_writeCount_mux0000_13_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(13),
      I1 => UUT_writeCount_share0000(13),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(13)
    );
  UUT_writeCount_mux0000_12_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(12),
      I1 => UUT_writeCount_share0000(12),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(12)
    );
  UUT_writeCount_mux0000_11_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(11),
      I1 => UUT_writeCount_share0000(11),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(11)
    );
  UUT_writeCount_mux0000_10_1 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_writeCount(10),
      I1 => UUT_writeCount_share0000(10),
      I2 => UUT_N35,
      I3 => UUT_N11,
      O => UUT_writeCount_mux0000(10)
    );
  UUT_Mtrien_in_i2c_mux000012 : LUT4
    generic map(
      INIT => X"CCCE"
    )
    port map (
      I0 => UUT_nstate_FFd1_509,
      I1 => UUT_nstate_cmp_eq0011,
      I2 => UUT_Mtridata_in_i2c_cmp_eq0003_336,
      I3 => N182,
      O => UUT_Mtrien_in_i2c_mux000012_355
    );
  UUT_ack_count_mux0000_9_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(9),
      I1 => UUT_ack_count_share0000(9),
      I2 => UUT_N14,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(9)
    );
  UUT_ack_count_mux0000_8_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(8),
      I1 => UUT_ack_count_share0000(8),
      I2 => UUT_N14,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(8)
    );
  UUT_ack_count_mux0000_7_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(7),
      I1 => UUT_ack_count_share0000(7),
      I2 => UUT_N14,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(7)
    );
  UUT_ack_count_mux0000_2_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(2),
      I1 => UUT_ack_count_share0000(2),
      I2 => UUT_N14,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(2)
    );
  UUT_ack_count_mux0000_1_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(1),
      I1 => UUT_ack_count_share0000(1),
      I2 => UUT_N14,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(1)
    );
  UUT_ack_count_mux0000_11_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(11),
      I1 => UUT_ack_count_share0000(11),
      I2 => UUT_N14,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(11)
    );
  UUT_ack_count_mux0000_10_1 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_ack_count(10),
      I1 => UUT_ack_count_share0000(10),
      I2 => UUT_N14,
      I3 => UUT_N3,
      O => UUT_ack_count_mux0000(10)
    );
  UUT_Mtridata_in_i2c_not000185 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_Mtridata_in_i2c_not000155_350,
      I1 => UUT_Mtridata_in_i2c_not000178_351,
      O => UUT_Mtridata_in_i2c_not000185_352
    );
  UUT_Dir_mux0000411 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_ack_count(8),
      I1 => UUT_ack_count(7),
      I2 => UUT_ack_count(2),
      O => UUT_N53
    );
  UUT_delay_count_mux0000_0_21 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => UUT_delay_count(1),
      I1 => UUT_delay_count(0),
      I2 => UUT_delay_count(5),
      I3 => UUT_N38,
      O => UUT_delay_count_and0000
    );
  UUT_shiftReg_cmp_eq00032_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => UUT_delay_count(6),
      I1 => UUT_delay_count(10),
      O => N33
    );
  UUT_shiftReg_or00002 : LUT4
    generic map(
      INIT => X"2E2F"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(7),
      I2 => UUT_delay_count(10),
      I3 => N35,
      O => UUT_N331
    );
  UUT_shiftReg_mux0000_4_0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_shiftReg(5),
      I1 => UUT_N12,
      O => UUT_shiftReg_mux0000_4_0_598
    );
  UUT_shiftReg_mux0000_4_3 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => N180,
      I1 => UUT_shiftReg(3),
      I2 => UUT_ClkRisingEdge_147,
      O => UUT_shiftReg_mux0000_4_3_600
    );
  UUT_shiftReg_mux0000_2_0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_shiftReg(3),
      I1 => UUT_N12,
      O => UUT_shiftReg_mux0000_2_0_592
    );
  UUT_shiftReg_or000017 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => UUT_delay_count(1),
      I1 => UUT_delay_count(4),
      I2 => UUT_delay_count(9),
      I3 => UUT_shiftReg_or000012_607,
      O => UUT_shiftReg_or000017_608
    );
  UUT_shiftReg_or000032 : LUT3
    generic map(
      INIT => X"0E"
    )
    port map (
      I0 => UUT_delay_count(0),
      I1 => UUT_delay_count(1),
      I2 => UUT_delay_count(10),
      O => UUT_shiftReg_or000032_609
    );
  UUT_shiftReg_mux0000_0_1311 : LUT4
    generic map(
      INIT => X"DDDC"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => UUT_shiftReg_mux0000_0_110_582,
      I2 => UUT_shiftReg_mux0000_0_113_583,
      I3 => N192,
      O => UUT_N0
    );
  UUT_shiftReg_mux0000_0_25 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => UUT_shiftReg_and0000,
      I2 => N189,
      O => UUT_shiftReg_mux0000_0_25_588
    );
  UUT_shiftReg_mux0000_0_216 : LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      I0 => UUT_delay_count(1),
      I1 => UUT_delay_count(0),
      I2 => UUT_N45,
      I3 => UUT_N33_376,
      O => UUT_shiftReg_mux0000_0_216_585
    );
  UUT_shiftReg_mux0000_0_244 : LUT4
    generic map(
      INIT => X"FFA8"
    )
    port map (
      I0 => UUT_N26,
      I1 => UUT_shiftReg_mux0000_0_216_585,
      I2 => UUT_shiftReg_mux0000_0_25_588,
      I3 => UUT_shiftReg_mux0000_0_240_587,
      O => UUT_N12
    );
  UUT_Mtrien_in_i2c_mux0000210 : LUT4
    generic map(
      INIT => X"BBFB"
    )
    port map (
      I0 => UUT_shiftReg_or0000,
      I1 => UUT_shiftReg_and0000,
      I2 => UUT_shiftReg_cmp_eq0000,
      I3 => UUT_shiftReg_cmp_eq0001,
      O => UUT_N31
    );
  UUT_Mtridata_in_i2c_mux000088 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => N183,
      I1 => UUT_Mtridata_in_i2c_mux000078_342,
      I2 => UUT_N55,
      I3 => UUT_Mtridata_in_i2c_cmp_eq0000,
      O => UUT_Mtridata_in_i2c_mux000088_343
    );
  UUT_shiftReg_cmp_eq00031 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_delay_count(8),
      I1 => UUT_delay_count(3),
      I2 => UUT_delay_count(15),
      I3 => N190,
      O => UUT_N38
    );
  SW_IBUF : IBUF
    port map (
      I => SW,
      O => SW_IBUF_142
    );
  I2C_Clk_OBUF : OBUF
    port map (
      I => UUT_out_i2cclk_528,
      O => I2C_Clk
    );
  UUT_nstate_FFd1 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_nstate_FFd1_In33,
      S => UUT_N68,
      Q => UUT_nstate_FFd1_509
    );
  UUT_nstate_FFd2 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_nstate_FFd2_In1_512,
      S => UUT_N68,
      Q => UUT_nstate_FFd2_511
    );
  UUT_nstate_FFd4 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_nstate_FFd4_In79,
      S => UUT_nstate_FFd4_In0_516,
      Q => UUT_nstate_FFd4_515
    );
  UUT_nstate_FFd4_In791 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => UUT_nstate_FFd4_In37_517,
      I1 => UUT_nstate_FFd4_In77_518,
      O => UUT_nstate_FFd4_In79
    );
  UUT_out_i2cclk : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_out_i2cclk_mux0000296,
      S => UUT_out_i2cclk_mux000055_542,
      Q => UUT_out_i2cclk_528
    );
  UUT_out_i2cclk_mux00002961 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => UUT_out_i2cclk_mux0000186_533,
      I1 => CLK_sI2C_Clk_23,
      I2 => UUT_out_i2cclk_mux0000270_540,
      O => UUT_out_i2cclk_mux0000296
    );
  UUT_ack_count_0 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ack_count_mux0000_0_73,
      S => UUT_ack_count_mux0000_0_39_412,
      Q => UUT_ack_count(0)
    );
  UUT_ack_count_mux0000_0_731 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => UUT_ack_count_mux0000_0_56_413,
      I1 => UUT_ack_count_share0000(0),
      I2 => UUT_N3,
      O => UUT_ack_count_mux0000_0_73
    );
  UUT_counter_0 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_counter_mux0000_4_24_449,
      S => UUT_counter_mux0000_4_11,
      Q => UUT_counter(0)
    );
  UUT_delay_count_0 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_delay_count_mux0000_0_25,
      S => UUT_delay_count_mux0000_0_18_471,
      Q => UUT_delay_count(0)
    );
  UUT_delay_count_mux0000_0_251 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_delay_count_share0000(0),
      I1 => UUT_N4,
      O => UUT_delay_count_mux0000_0_25
    );
  UUT_ClkRisingEdge : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_ClkRisingEdge_and00001,
      R => UUT_prevClk_545,
      Q => UUT_ClkRisingEdge_147
    );
  UUT_ClkRisingEdge_and000011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => UUT_ClkEdge(1),
      I1 => UUT_ClkEdge(0),
      O => UUT_ClkRisingEdge_and00001
    );
  UUT_shiftReg_7 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_7_1_605,
      S => UUT_nstate_cmp_eq0005,
      Q => UUT_shiftReg(7)
    );
  UUT_shiftReg_6 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_6_18,
      S => UUT_shiftReg_mux0000_6_5_604,
      Q => UUT_shiftReg(6)
    );
  UUT_shiftReg_5 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_5_1_601,
      S => UUT_nstate_cmp_eq0005,
      Q => UUT_shiftReg(5)
    );
  UUT_shiftReg_mux0000_5_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => UUT_shiftReg(5),
      I1 => UUT_N0,
      I2 => N47,
      O => UUT_shiftReg_mux0000_5_1_601
    );
  UUT_shiftReg_4 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_4_11,
      S => UUT_shiftReg_mux0000_4_0_598,
      Q => UUT_shiftReg(4)
    );
  UUT_shiftReg_3 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_3_23,
      S => UUT_shiftReg_mux0000_3_8_597,
      Q => UUT_shiftReg(3)
    );
  UUT_shiftReg_2 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_2_11,
      S => UUT_shiftReg_mux0000_2_0_592,
      Q => UUT_shiftReg(2)
    );
  UUT_shiftReg_1 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_1_1_591,
      S => UUT_nstate_cmp_eq0005,
      Q => UUT_shiftReg(1)
    );
  UUT_shiftReg_mux0000_1_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => UUT_shiftReg(1),
      I1 => UUT_N0,
      I2 => N49,
      O => UUT_shiftReg_mux0000_1_1_591
    );
  UUT_shiftReg_0 : FDS
    generic map(
      INIT => '0'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_shiftReg_mux0000_0_23,
      S => UUT_shiftReg_mux0000_0_8_590,
      Q => UUT_shiftReg(0)
    );
  UUT_Dir : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => FPGA_Clk_BUFGP_29,
      D => UUT_Dir_mux0000224,
      S => UUT_Dir_mux000061,
      Q => UUT_Dir_149
    );
  CLK_Mcount_clk_div_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => CLK_clk_div(1),
      O => CLK_Mcount_clk_div_cy_1_rt_2
    );
  CLK_Mcount_clk_div_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => CLK_clk_div(2),
      O => CLK_Mcount_clk_div_cy_2_rt_4
    );
  CLK_Mcount_clk_div_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => CLK_clk_div(3),
      O => CLK_Mcount_clk_div_cy_3_rt_6
    );
  CLK_Mcount_clk_div_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => CLK_clk_div(4),
      O => CLK_Mcount_clk_div_cy_4_rt_8
    );
  CLK_Mcount_clk_div_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => CLK_clk_div(5),
      O => CLK_Mcount_clk_div_cy_5_rt_10
    );
  CLK_Mcount_clk_div_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => CLK_clk_div(6),
      O => CLK_Mcount_clk_div_cy_6_rt_12
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(8),
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_4_rt_280
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(2),
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_0_rt_275
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(4),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_0_rt_310
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(8),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_rt_315
    );
  UUT_Madd_ack_count_share0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(10),
      O => UUT_Madd_ack_count_share0000_cy_10_rt_160
    );
  UUT_Madd_ack_count_share0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(9),
      O => UUT_Madd_ack_count_share0000_cy_9_rt_178
    );
  UUT_Madd_ack_count_share0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(8),
      O => UUT_Madd_ack_count_share0000_cy_8_rt_176
    );
  UUT_Madd_ack_count_share0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(7),
      O => UUT_Madd_ack_count_share0000_cy_7_rt_174
    );
  UUT_Madd_ack_count_share0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(6),
      O => UUT_Madd_ack_count_share0000_cy_6_rt_172
    );
  UUT_Madd_ack_count_share0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(5),
      O => UUT_Madd_ack_count_share0000_cy_5_rt_170
    );
  UUT_Madd_ack_count_share0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(4),
      O => UUT_Madd_ack_count_share0000_cy_4_rt_168
    );
  UUT_Madd_ack_count_share0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(3),
      O => UUT_Madd_ack_count_share0000_cy_3_rt_166
    );
  UUT_Madd_ack_count_share0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(2),
      O => UUT_Madd_ack_count_share0000_cy_2_rt_164
    );
  UUT_Madd_ack_count_share0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(1),
      O => UUT_Madd_ack_count_share0000_cy_1_rt_162
    );
  UUT_Madd_delay_count_share0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(14),
      O => UUT_Madd_delay_count_share0000_cy_14_rt_192
    );
  UUT_Madd_delay_count_share0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(13),
      O => UUT_Madd_delay_count_share0000_cy_13_rt_190
    );
  UUT_Madd_delay_count_share0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(12),
      O => UUT_Madd_delay_count_share0000_cy_12_rt_188
    );
  UUT_Madd_delay_count_share0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(11),
      O => UUT_Madd_delay_count_share0000_cy_11_rt_186
    );
  UUT_Madd_delay_count_share0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(10),
      O => UUT_Madd_delay_count_share0000_cy_10_rt_184
    );
  UUT_Madd_delay_count_share0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(9),
      O => UUT_Madd_delay_count_share0000_cy_9_rt_210
    );
  UUT_Madd_delay_count_share0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(8),
      O => UUT_Madd_delay_count_share0000_cy_8_rt_208
    );
  UUT_Madd_delay_count_share0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(7),
      O => UUT_Madd_delay_count_share0000_cy_7_rt_206
    );
  UUT_Madd_delay_count_share0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(6),
      O => UUT_Madd_delay_count_share0000_cy_6_rt_204
    );
  UUT_Madd_delay_count_share0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(5),
      O => UUT_Madd_delay_count_share0000_cy_5_rt_202
    );
  UUT_Madd_delay_count_share0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(4),
      O => UUT_Madd_delay_count_share0000_cy_4_rt_200
    );
  UUT_Madd_delay_count_share0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(3),
      O => UUT_Madd_delay_count_share0000_cy_3_rt_198
    );
  UUT_Madd_delay_count_share0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(2),
      O => UUT_Madd_delay_count_share0000_cy_2_rt_196
    );
  UUT_Madd_delay_count_share0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(1),
      O => UUT_Madd_delay_count_share0000_cy_1_rt_194
    );
  UUT_Madd_writeCount_share0000_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(29),
      O => UUT_Madd_writeCount_share0000_cy_29_rt_255
    );
  UUT_Madd_writeCount_share0000_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(28),
      O => UUT_Madd_writeCount_share0000_cy_28_rt_253
    );
  UUT_Madd_writeCount_share0000_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(27),
      O => UUT_Madd_writeCount_share0000_cy_27_rt_251
    );
  UUT_Madd_writeCount_share0000_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(26),
      O => UUT_Madd_writeCount_share0000_cy_26_rt_249
    );
  UUT_Madd_writeCount_share0000_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(25),
      O => UUT_Madd_writeCount_share0000_cy_25_rt_247
    );
  UUT_Madd_writeCount_share0000_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(24),
      O => UUT_Madd_writeCount_share0000_cy_24_rt_245
    );
  UUT_Madd_writeCount_share0000_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(23),
      O => UUT_Madd_writeCount_share0000_cy_23_rt_243
    );
  UUT_Madd_writeCount_share0000_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(22),
      O => UUT_Madd_writeCount_share0000_cy_22_rt_241
    );
  UUT_Madd_writeCount_share0000_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(21),
      O => UUT_Madd_writeCount_share0000_cy_21_rt_239
    );
  UUT_Madd_writeCount_share0000_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(20),
      O => UUT_Madd_writeCount_share0000_cy_20_rt_237
    );
  UUT_Madd_writeCount_share0000_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(19),
      O => UUT_Madd_writeCount_share0000_cy_19_rt_233
    );
  UUT_Madd_writeCount_share0000_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(18),
      O => UUT_Madd_writeCount_share0000_cy_18_rt_231
    );
  UUT_Madd_writeCount_share0000_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(17),
      O => UUT_Madd_writeCount_share0000_cy_17_rt_229
    );
  UUT_Madd_writeCount_share0000_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(16),
      O => UUT_Madd_writeCount_share0000_cy_16_rt_227
    );
  UUT_Madd_writeCount_share0000_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(15),
      O => UUT_Madd_writeCount_share0000_cy_15_rt_225
    );
  UUT_Madd_writeCount_share0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(14),
      O => UUT_Madd_writeCount_share0000_cy_14_rt_223
    );
  UUT_Madd_writeCount_share0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(13),
      O => UUT_Madd_writeCount_share0000_cy_13_rt_221
    );
  UUT_Madd_writeCount_share0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(12),
      O => UUT_Madd_writeCount_share0000_cy_12_rt_219
    );
  UUT_Madd_writeCount_share0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(11),
      O => UUT_Madd_writeCount_share0000_cy_11_rt_217
    );
  UUT_Madd_writeCount_share0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(10),
      O => UUT_Madd_writeCount_share0000_cy_10_rt_215
    );
  UUT_Madd_writeCount_share0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(9),
      O => UUT_Madd_writeCount_share0000_cy_9_rt_271
    );
  UUT_Madd_writeCount_share0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(8),
      O => UUT_Madd_writeCount_share0000_cy_8_rt_269
    );
  UUT_Madd_writeCount_share0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(7),
      O => UUT_Madd_writeCount_share0000_cy_7_rt_267
    );
  UUT_Madd_writeCount_share0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(6),
      O => UUT_Madd_writeCount_share0000_cy_6_rt_265
    );
  UUT_Madd_writeCount_share0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(5),
      O => UUT_Madd_writeCount_share0000_cy_5_rt_263
    );
  UUT_Madd_writeCount_share0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(4),
      O => UUT_Madd_writeCount_share0000_cy_4_rt_261
    );
  UUT_Madd_writeCount_share0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(3),
      O => UUT_Madd_writeCount_share0000_cy_3_rt_259
    );
  UUT_Madd_writeCount_share0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(2),
      O => UUT_Madd_writeCount_share0000_cy_2_rt_257
    );
  UUT_Madd_writeCount_share0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(1),
      O => UUT_Madd_writeCount_share0000_cy_1_rt_235
    );
  CLK_Mcount_clk_div_xor_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => CLK_clk_div(7),
      O => CLK_Mcount_clk_div_xor_7_rt_14
    );
  UUT_Madd_ack_count_share0000_xor_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_ack_count(11),
      O => UUT_Madd_ack_count_share0000_xor_11_rt_180
    );
  UUT_Madd_delay_count_share0000_xor_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_delay_count(15),
      O => UUT_Madd_delay_count_share0000_xor_15_rt_212
    );
  UUT_Madd_writeCount_share0000_xor_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_writeCount(30),
      O => UUT_Madd_writeCount_share0000_xor_30_rt_273
    );
  UUT_pstate_mux0000_5_1111 : LUT4
    generic map(
      INIT => X"FFF4"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0000_520,
      I1 => UUT_nstate_cmp_eq0010,
      I2 => UUT_pstate_mux0000_5_1110_550,
      I3 => UUT_N68,
      O => UUT_pstate_mux0000_5_1111_551
    );
  UUT_shiftReg_mux0000_6_181 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_shiftReg(6),
      I1 => UUT_shiftReg(7),
      I2 => UUT_N12,
      I3 => UUT_N0,
      O => UUT_shiftReg_mux0000_6_18
    );
  UUT_shiftReg_mux0000_3_231 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_shiftReg(3),
      I1 => UUT_shiftReg(4),
      I2 => UUT_N12,
      I3 => UUT_N0,
      O => UUT_shiftReg_mux0000_3_23
    );
  UUT_shiftReg_mux0000_0_231 : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_shiftReg(1),
      I1 => UUT_shiftReg(0),
      I2 => UUT_N12,
      I3 => UUT_N0,
      O => UUT_shiftReg_mux0000_0_23
    );
  UUT_shiftReg_and00001_SW0 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => UUT_delay_count(5),
      I1 => UUT_delay_count(2),
      O => N56
    );
  UUT_delay_count_mux0000_0_21_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_delay_count(1),
      I1 => UUT_delay_count(5),
      I2 => UUT_delay_count(0),
      I3 => UUT_delay_count(2),
      O => N62
    );
  UUT_shiftReg_mux0000_0_111 : LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      I0 => N62,
      I1 => UUT_shiftReg_cmp_eq0001,
      I2 => UUT_N38,
      I3 => N187,
      O => UUT_N13
    );
  UUT_out_i2cclk_mux000081 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(9),
      I1 => UUT_ack_count(8),
      I2 => UUT_ack_count(7),
      I3 => N64,
      O => UUT_ack_count_and0025
    );
  UUT_Mtridata_in_i2c_mux0000121 : LUT4
    generic map(
      INIT => X"F5E4"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0006,
      I1 => UUT_Mtridata_in_i2c_mux000088_343,
      I2 => UUT_Mtridata_in_i2c_cmp_eq0000,
      I3 => UUT_Mtridata_in_i2c_mux000065_341,
      O => UUT_Mtridata_in_i2c_mux0000
    );
  UUT_Mtridata_in_i2c_mux000022 : LUT4
    generic map(
      INIT => X"F8B8"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0002,
      I1 => UUT_shiftReg_and0000,
      I2 => UUT_Mtridata_in_i2c_mux000011_338,
      I3 => UUT_shiftReg_or0000,
      O => UUT_Mtridata_in_i2c_mux000022_339
    );
  UUT_shiftReg_and00001 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => N51,
      I1 => UUT_delay_count(8),
      I2 => UUT_delay_count(5),
      I3 => N68,
      O => UUT_shiftReg_and0000
    );
  UUT_shiftReg_mux0000_0_1311_SW1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => UUT_shiftReg(7),
      I1 => UUT_ClkFallingEdge_145,
      I2 => UUT_shiftReg_mux0000_0_110_582,
      O => N71
    );
  UUT_shiftReg_mux0000_7_1 : LUT4
    generic map(
      INIT => X"EFEC"
    )
    port map (
      I0 => N71,
      I1 => N45,
      I2 => UUT_shiftReg_mux0000_0_113_583,
      I3 => N70,
      O => UUT_shiftReg_mux0000_7_1_605
    );
  UUT_shiftReg_mux0000_0_1311_SW2 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => UUT_shiftReg_mux0000_4_3_600,
      I1 => UUT_shiftReg_mux0000_0_110_582,
      I2 => UUT_shiftReg(4),
      O => N73
    );
  UUT_shiftReg_mux0000_4_111 : LUT4
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => N74,
      I1 => UUT_shiftReg_mux0000_0_113_583,
      I2 => UUT_shiftReg_mux0000_0_116_584,
      I3 => N73,
      O => UUT_shiftReg_mux0000_4_11
    );
  UUT_shiftReg_mux0000_0_1311_SW4 : LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      I0 => N188,
      I1 => UUT_shiftReg_mux0000_0_110_582,
      I2 => UUT_shiftReg(2),
      O => N76
    );
  UUT_shiftReg_mux0000_2_111 : LUT4
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => N77,
      I1 => UUT_shiftReg_mux0000_0_113_583,
      I2 => UUT_shiftReg_mux0000_0_116_584,
      I3 => N76,
      O => UUT_shiftReg_mux0000_2_11
    );
  UUT_shiftReg_mux0000_0_113 : LUT4
    generic map(
      INIT => X"AA2A"
    )
    port map (
      I0 => UUT_N26,
      I1 => UUT_shiftReg_and0000,
      I2 => N79,
      I3 => UUT_shiftReg_or0000,
      O => UUT_shiftReg_mux0000_0_113_583
    );
  UUT_Mtridata_in_i2c_cmp_eq000211 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(6),
      I3 => UUT_ack_count(3),
      O => UUT_N70
    );
  UUT_Mtridata_in_i2c_cmp_eq0003_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(0),
      O => N31
    );
  UUT_Dir_mux00002241 : LUT4
    generic map(
      INIT => X"FAF8"
    )
    port map (
      I0 => UUT_Dir_149,
      I1 => UUT_Dir_mux0000127_151,
      I2 => UUT_Dir_mux000082_157,
      I3 => N81,
      O => UUT_Dir_mux0000224
    );
  UUT_Dir_mux00002_SW0_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(5),
      I2 => UUT_ack_count(2),
      I3 => UUT_ack_count(8),
      O => N83
    );
  UUT_out_i2cclk_mux000051 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(3),
      I3 => N186,
      O => UUT_N42
    );
  UUT_pstate_mux0000_5_1180 : LUT4
    generic map(
      INIT => X"40C8"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_N72,
      I2 => UUT_Mcompar_nstate_cmp_gt0000_cy(4),
      I3 => N185,
      O => UUT_pstate_mux0000_5_1180_553
    );
  UUT_out_i2cclk_mux0000213 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => UUT_ack_count(1),
      I1 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1,
      I2 => N191,
      O => UUT_out_i2cclk_mux0000213_538
    );
  UUT_shiftReg_cmp_eq00001 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_delay_count(6),
      I1 => UUT_delay_count(4),
      I2 => UUT_delay_count(10),
      I3 => N87,
      O => UUT_shiftReg_cmp_eq0000
    );
  UUT_Mtrien_in_i2c_mux000078 : MUXF5
    port map (
      I0 => N89,
      I1 => N90,
      S => UUT_nstate_cmp_eq0006,
      O => UUT_Mtrien_in_i2c_mux0000
    );
  UUT_Mtrien_in_i2c_mux000078_F : LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      I0 => UUT_Mtrien_in_i2c_mux000024_356,
      I1 => UUT_N55,
      I2 => UUT_N31,
      I3 => UUT_Mtrien_in_i2c_mux000012_355,
      O => N89
    );
  UUT_Mtrien_in_i2c_mux000078_G : LUT4
    generic map(
      INIT => X"A2AA"
    )
    port map (
      I0 => UUT_Mtrien_in_i2c_mux000062_357,
      I1 => UUT_N70,
      I2 => UUT_ack_count(0),
      I3 => UUT_ack_count_and0025,
      O => N90
    );
  UUT_Mtridata_in_i2c_not000137 : LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      I0 => UUT_nstate_FFd1_509,
      I1 => UUT_nstate_FFd4_515,
      I2 => N91,
      I3 => UUT_N42,
      O => UUT_Mtridata_in_i2c_not000137_349
    );
  UUT_nstate_FFd3_In_SW0 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_Mcompar_nstate_cmp_gt0000_cy(4),
      I2 => UUT_nstate_FFd2_511,
      O => N12
    );
  UUT_Mtridata_in_i2c_not0001200 : LUT4
    generic map(
      INIT => X"2F22"
    )
    port map (
      I0 => UUT_delay_count_or0001,
      I1 => UUT_nstate_FFd1_509,
      I2 => UUT_N41,
      I3 => UUT_Mtridata_in_i2c_not0001176_348,
      O => UUT_Mtridata_in_i2c_not0001
    );
  UUT_out_i2cclk_mux0000186 : LUT4
    generic map(
      INIT => X"A222"
    )
    port map (
      I0 => UUT_out_i2cclk_528,
      I1 => UUT_N32,
      I2 => UUT_out_i2cclk_mux0000145_531,
      I3 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1,
      O => UUT_out_i2cclk_mux0000186_533
    );
  UUT_N392 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_ack_count(11),
      I1 => UUT_ack_count(10),
      I2 => UUT_ack_count(9),
      I3 => N93,
      O => UUT_N392_384
    );
  UUT_ack_count_mux0000_0_39_SW0 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => N194,
      I1 => UUT_ClkFallingEdge_145,
      I2 => UUT_nstate_FFd1_509,
      I3 => UUT_ClkRisingEdge_147,
      O => N97
    );
  UUT_ack_count_mux0000_0_39 : LUT4
    generic map(
      INIT => X"88F8"
    )
    port map (
      I0 => UUT_ack_count_mux0000_0_23_411,
      I1 => N97,
      I2 => UUT_ack_count(0),
      I3 => UUT_N32,
      O => UUT_ack_count_mux0000_0_39_412
    );
  UUT_N3157_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_ack_count(1),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(3),
      I3 => UUT_ack_count(0),
      O => N102
    );
  UUT_out_i2cclk_mux0000237 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => UUT_N42,
      I1 => UUT_ack_count(11),
      I2 => UUT_ack_count(10),
      I3 => N104,
      O => UUT_out_i2cclk_mux0000237_539
    );
  UUT_Dir_mux0000611 : LUT4
    generic map(
      INIT => X"F080"
    )
    port map (
      I0 => UUT_N62,
      I1 => N106,
      I2 => UUT_Dir_mux000058_155,
      I3 => UUT_Dir_mux000011_150,
      O => UUT_Dir_mux000061
    );
  UUT_shiftReg_mux0000_6_5 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0008,
      I1 => UUT_shiftReg_and0000,
      I2 => UUT_shiftReg_cmp_eq0002,
      I3 => UUT_shiftReg_mux0000_6_3_603,
      O => UUT_shiftReg_mux0000_6_5_604
    );
  UUT_Mtrien_in_i2c_mux000024 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => N178,
      I2 => UUT_Mtrien_in_i2c_353,
      I3 => UUT_ClkFallingEdge_145,
      O => UUT_Mtrien_in_i2c_mux000024_356
    );
  UUT_shiftReg_mux0000_0_211 : LUT3
    generic map(
      INIT => X"48"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd4_515,
      O => UUT_N26
    );
  UUT_ack_count_mux0000_0_23_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_ack_count(2),
      I1 => UUT_ack_count(1),
      I2 => UUT_ack_count(8),
      I3 => UUT_ack_count(0),
      O => N108
    );
  UUT_nstate_Out11 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd2_511,
      O => UUT_nstate_cmp_eq0006
    );
  UUT_N327 : LUT4
    generic map(
      INIT => X"3332"
    )
    port map (
      I0 => UUT_ack_count(3),
      I1 => UUT_ack_count(6),
      I2 => UUT_ack_count(0),
      I3 => UUT_ack_count(4),
      O => UUT_N327_375
    );
  UUT_nstate_Out01 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_nstate_FFd4_515,
      O => UUT_nstate_cmp_eq0005
    );
  UUT_out_i2cclk_mux000017 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(3),
      I1 => UUT_ack_count(0),
      I2 => UUT_ack_count(6),
      I3 => UUT_nstate_FFd3_513,
      O => UUT_out_i2cclk_mux000017_532
    );
  UUT_Mtridata_in_i2c_not0001162 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(8),
      I1 => UUT_ack_count(7),
      I2 => UUT_ack_count(2),
      I3 => UUT_ack_count(0),
      O => UUT_Mtridata_in_i2c_not0001162_347
    );
  UUT_out_i2cclk_mux0000210 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd4_515,
      I3 => UUT_nstate_FFd1_509,
      O => UUT_out_i2cclk_mux0000210_537
    );
  UUT_delay_count_mux0000_0_0 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => UUT_delay_count(0),
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd1_509,
      O => UUT_delay_count_mux0000_0_0_467
    );
  UUT_writeCount_mux0000_0_SW0 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => UUT_writeCount(0),
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd1_509,
      O => N20
    );
  UUT_pstate_mux0000_5_1110 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_Mcompar_nstate_cmp_gt0002_cy(7),
      O => UUT_pstate_mux0000_5_1110_550
    );
  UUT_shiftReg_mux0000_3_8 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0008,
      I1 => UUT_shiftReg_and0000,
      I2 => UUT_shiftReg_cmp_eq0002,
      I3 => UUT_shiftReg_mux0000_3_5_596,
      O => UUT_shiftReg_mux0000_3_8_597
    );
  UUT_shiftReg_mux0000_0_8 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => UUT_N26,
      I1 => UUT_shiftReg_and0000,
      I2 => UUT_shiftReg_cmp_eq0002,
      I3 => UUT_shiftReg_mux0000_0_5_589,
      O => UUT_shiftReg_mux0000_0_8_590
    );
  UUT_Mtrien_in_i2c_mux000062 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => UUT_N67,
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(5),
      I3 => UUT_ack_count_and0025,
      O => UUT_Mtrien_in_i2c_mux000062_357
    );
  UUT_Dir_mux000058 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(3),
      I3 => UUT_N41,
      O => UUT_Dir_mux000058_155
    );
  UUT_ack_count_mux0000_10_229 : LUT4
    generic map(
      INIT => X"5703"
    )
    port map (
      I0 => UUT_ClkRisingEdge_147,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_ack_count_mux0000_10_212_416,
      O => UUT_N14
    );
  UUT_nstate_FFd3_In : LUT4
    generic map(
      INIT => X"EEE4"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => N12,
      I2 => UUT_Mcompar_nstate_cmp_gt0002_cy(5),
      I3 => N13,
      O => UUT_nstate_FFd3_In_514
    );
  UUT_pstate_mux0000_6_SW1 : LUT4
    generic map(
      INIT => X"B5FF"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy(7),
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_nstate_FFd3_513,
      O => N40
    );
  UUT_pstate_mux0000_5_SW1 : LUT4
    generic map(
      INIT => X"2820"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_Mcompar_nstate_cmp_gt0002_cy(7),
      O => N43
    );
  UUT_N3106 : LUT4
    generic map(
      INIT => X"AF23"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => N119,
      I2 => UUT_ack_count(8),
      I3 => UUT_ack_count(2),
      O => UUT_N3106_370
    );
  UUT_pstate_mux0000_5_112_SW0 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(3),
      I3 => UUT_ack_count(0),
      O => N121
    );
  UUT_pstate_mux0000_5_112 : LUT4
    generic map(
      INIT => X"4CCC"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_nstate_FFd1_509,
      I2 => N121,
      I3 => UUT_ack_count_and0025,
      O => UUT_N68
    );
  UUT_Dir_mux000011 : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count(7),
      I2 => UUT_ack_count(2),
      I3 => N125,
      O => UUT_Dir_mux000011_150
    );
  UUT_Mtridata_in_i2c_not0001137_SW2 : LUT3
    generic map(
      INIT => X"F6"
    )
    port map (
      I0 => UUT_ack_count(1),
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_ack_count(4),
      O => N127
    );
  UUT_Mtridata_in_i2c_not0001137_SW3 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => UUT_nstate_FFd1_509,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_ack_count(4),
      I3 => UUT_ack_count(1),
      O => N128
    );
  UUT_Mtridata_in_i2c_not0001137 : LUT4
    generic map(
      INIT => X"028A"
    )
    port map (
      I0 => UUT_Mtridata_in_i2c_not0001134_345,
      I1 => UUT_ack_count(5),
      I2 => N127,
      I3 => N128,
      O => UUT_Mtridata_in_i2c_not0001137_346
    );
  UUT_shiftReg_mux0000_7_SW0 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => UUT_shiftReg_and0000,
      I1 => UUT_shiftReg_cmp_eq0002,
      I2 => UUT_N26,
      I3 => N132,
      O => N45
    );
  UUT_Dir_mux000091 : LUT3
    generic map(
      INIT => X"C8"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd4_515,
      O => UUT_delay_count_or0001
    );
  UUT_Mtridata_in_i2c_mux000078 : LUT4
    generic map(
      INIT => X"A2AA"
    )
    port map (
      I0 => UUT_nstate_FFd1_509,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_nstate_FFd3_513,
      I3 => UUT_nstate_FFd4_515,
      O => UUT_Mtridata_in_i2c_mux000078_342
    );
  UUT_counter_mux0000_4_24_SW0 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => UUT_counter(3),
      I1 => UUT_counter(2),
      I2 => UUT_counter(4),
      I3 => UUT_counter(1),
      O => N134
    );
  UUT_counter_mux0000_4_24 : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd3_513,
      I3 => N134,
      O => UUT_counter_mux0000_4_24_449
    );
  UUT_ack_count_mux0000_10_212_SW1 : LUT4
    generic map(
      INIT => X"3331"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd1_509,
      I2 => UUT_nstate_FFd3_513,
      I3 => UUT_nstate_FFd2_511,
      O => N136
    );
  UUT_Dir_mux000082_SW1 : LUT4
    generic map(
      INIT => X"FF57"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_delay_count(2),
      O => N138
    );
  UUT_Dir_mux000082 : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => UUT_N38,
      I1 => UUT_shiftReg_cmp_eq0002,
      I2 => UUT_delay_count(5),
      I3 => N138,
      O => UUT_Dir_mux000082_157
    );
  UUT_delay_count_mux0000_11_1 : LUT4
    generic map(
      INIT => X"FFD5"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_delay_count_and0000,
      I2 => N140,
      I3 => UUT_nstate_FFd1_509,
      O => UUT_N15
    );
  UUT_Dir_mux0000194_SW0_SW1 : LUT4
    generic map(
      INIT => X"397D"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_ack_count(1),
      I3 => UUT_nstate_FFd1_509,
      O => N142
    );
  UUT_Dir_mux0000194_SW0 : LUT4
    generic map(
      INIT => X"EE4E"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => N142,
      I2 => UUT_N38,
      I3 => N143,
      O => N81
    );
  UUT_shiftReg_mux0000_0_110 : LUT4
    generic map(
      INIT => X"F4FE"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => N145,
      I2 => UUT_nstate_FFd1_509,
      I3 => UUT_nstate_FFd3_513,
      O => UUT_shiftReg_mux0000_0_110_582
    );
  UUT_delay_count_mux0000_0_170 : LUT4
    generic map(
      INIT => X"8A02"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_N32,
      I2 => UUT_Mcompar_delay_count_cmp_lt0000_cy(6),
      I3 => UUT_delay_count_mux0000_0_146_470,
      O => UUT_N4
    );
  UUT_out_i2cclk_mux0000115 : MUXF5
    port map (
      I0 => N149,
      I1 => N150,
      S => UUT_ack_count(7),
      O => UUT_out_i2cclk_mux0000115_529
    );
  UUT_out_i2cclk_mux0000115_F : LUT4
    generic map(
      INIT => X"7F72"
    )
    port map (
      I0 => UUT_ack_count(2),
      I1 => UUT_ack_count(1),
      I2 => UUT_ack_count(3),
      I3 => UUT_ack_count(6),
      O => N149
    );
  UUT_out_i2cclk_mux0000115_G : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(3),
      I2 => UUT_ack_count(2),
      I3 => UUT_ack_count(1),
      O => N150
    );
  UUT_counter_mux0000_1_Q : MUXF5
    port map (
      I0 => N151,
      I1 => N152,
      S => UUT_Madd_counter_addsub0000_cy(2),
      O => UUT_counter_mux0000(1)
    );
  UUT_counter_mux0000_1_F : LUT3
    generic map(
      INIT => X"C8"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_counter(3),
      I2 => UUT_N121,
      O => N151
    );
  UUT_counter_mux0000_1_G : LUT4
    generic map(
      INIT => X"EC20"
    )
    port map (
      I0 => UUT_ClkRisingEdge_147,
      I1 => UUT_counter(3),
      I2 => UUT_nstate_cmp_eq0010,
      I3 => UUT_N121,
      O => N152
    );
  UUT_counter_mux0000_3_Q : MUXF5
    port map (
      I0 => N153,
      I1 => N154,
      S => UUT_counter(1),
      O => UUT_counter_mux0000(3)
    );
  UUT_counter_mux0000_3_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => UUT_ClkRisingEdge_147,
      I1 => UUT_nstate_cmp_eq0010,
      I2 => UUT_counter(0),
      O => N153
    );
  UUT_counter_mux0000_3_G : LUT3
    generic map(
      INIT => X"F4"
    )
    port map (
      I0 => UUT_counter(0),
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_N121,
      O => N154
    );
  UUT_Mtridata_in_i2c_mux000037 : MUXF5
    port map (
      I0 => N155,
      I1 => N156,
      S => UUT_shiftReg_cmp_eq0001,
      O => UUT_Mtridata_in_i2c_mux000037_340
    );
  UUT_Mtridata_in_i2c_mux000037_F : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => UUT_Mtridata_in_i2c_334,
      I2 => UUT_shiftReg(0),
      O => N155
    );
  UUT_Mtridata_in_i2c_mux000037_G : LUT4
    generic map(
      INIT => X"F080"
    )
    port map (
      I0 => UUT_N38,
      I1 => N56,
      I2 => UUT_shiftReg(0),
      I3 => UUT_ClkFallingEdge_145,
      O => N156
    );
  UUT_pstate_mux0000_5_1143 : MUXF5
    port map (
      I0 => N157,
      I1 => N158,
      S => UUT_nstate_FFd3_513,
      O => UUT_pstate_mux0000_5_1143_552
    );
  UUT_pstate_mux0000_5_1143_F : LUT4
    generic map(
      INIT => X"0203"
    )
    port map (
      I0 => CLK_sI2C_Clk_23,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_nstate_FFd4_515,
      I3 => SW_IBUF_142,
      O => N157
    );
  UUT_pstate_mux0000_5_1143_G : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy(5),
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_nstate_FFd4_515,
      O => N158
    );
  UUT_nstate_FFd2_In1 : MUXF5
    port map (
      I0 => N159,
      I1 => N160,
      S => UUT_nstate_FFd3_513,
      O => UUT_nstate_FFd2_In1_512
    );
  UUT_nstate_FFd2_In1_F : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd1_509,
      I2 => UUT_nstate_FFd4_515,
      O => N159
    );
  UUT_nstate_FFd2_In1_G : LUT4
    generic map(
      INIT => X"888D"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy(7),
      I2 => UUT_nstate_FFd4_515,
      I3 => UUT_Mcompar_nstate_cmp_gt0002_cy(5),
      O => N160
    );
  UUT_pstate_mux0000_6_Q : MUXF5
    port map (
      I0 => N161,
      I1 => N162,
      S => UUT_pstate(2),
      O => UUT_pstate_mux0000(6)
    );
  UUT_pstate_mux0000_6_F : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => UUT_N60,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_Mcompar_nstate_cmp_gt0002_cy(7),
      O => N161
    );
  UUT_pstate_mux0000_6_G : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => UUT_pstate_mux0000_5_1143_552,
      I1 => UUT_pstate_mux0000_5_1180_553,
      I2 => N40,
      I3 => UUT_pstate_mux0000_5_1111_551,
      O => N162
    );
  UUT_pstate_mux0000_5_Q : MUXF5
    port map (
      I0 => N163,
      I1 => N164,
      S => UUT_pstate(3),
      O => UUT_pstate_mux0000(5)
    );
  UUT_pstate_mux0000_5_F : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0008,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy(7),
      O => N163
    );
  UUT_pstate_mux0000_5_G : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_pstate_mux0000_5_1111_551,
      I1 => UUT_pstate_mux0000_5_1180_553,
      I2 => N43,
      I3 => UUT_pstate_mux0000_5_1143_552,
      O => N164
    );
  UUT_Mtridata_in_i2c_not000178 : MUXF5
    port map (
      I0 => N165,
      I1 => N166,
      S => UUT_ack_count(6),
      O => UUT_Mtridata_in_i2c_not000178_351
    );
  UUT_Mtridata_in_i2c_not000178_F : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(3),
      O => N165
    );
  UUT_Mtridata_in_i2c_not000178_G : LUT4
    generic map(
      INIT => X"0801"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(1),
      I3 => UUT_ack_count(3),
      O => N166
    );
  UUT_counter_mux0000_0_Q : MUXF5
    port map (
      I0 => N167,
      I1 => N168,
      S => UUT_counter(4),
      O => UUT_counter_mux0000(0)
    );
  UUT_counter_mux0000_0_F : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0010,
      I1 => UUT_Madd_counter_addsub0000_cy(2),
      I2 => UUT_counter(3),
      I3 => UUT_ClkRisingEdge_147,
      O => N167
    );
  UUT_counter_mux0000_0_G : LUT4
    generic map(
      INIT => X"FF4C"
    )
    port map (
      I0 => UUT_Madd_counter_addsub0000_cy(2),
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_counter(3),
      I3 => UUT_N121,
      O => N168
    );
  UUT_counter_mux0000_2_Q : MUXF5
    port map (
      I0 => N169,
      I1 => N170,
      S => UUT_counter(2),
      O => UUT_counter_mux0000(2)
    );
  UUT_counter_mux0000_2_F : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0010,
      I1 => UUT_ClkRisingEdge_147,
      I2 => UUT_counter(1),
      I3 => UUT_counter(0),
      O => N169
    );
  UUT_counter_mux0000_2_G : LUT4
    generic map(
      INIT => X"FF4C"
    )
    port map (
      I0 => UUT_counter(1),
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_counter(0),
      I3 => UUT_N121,
      O => N170
    );
  UUT_nstate_FFd4_In37 : MUXF5
    port map (
      I0 => N171,
      I1 => N172,
      S => UUT_nstate_FFd3_513,
      O => UUT_nstate_FFd4_In37_517
    );
  UUT_nstate_FFd4_In37_F : LUT4
    generic map(
      INIT => X"2232"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd2_511,
      I2 => SW_IBUF_142,
      I3 => CLK_sI2C_Clk_23,
      O => N171
    );
  UUT_nstate_FFd4_In37_G : LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => UUT_pstate(3),
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_Mcompar_nstate_cmp_gt0002_cy(5),
      I3 => UUT_nstate_FFd2_511,
      O => N172
    );
  UUT_out_i2cclk_mux000020 : MUXF5
    port map (
      I0 => N173,
      I1 => N174,
      S => UUT_ack_count(5),
      O => UUT_out_i2cclk_mux000020_535
    );
  UUT_out_i2cclk_mux000020_F : LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => UUT_out_i2cclk_528,
      I1 => UUT_out_i2cclk_mux000017_532,
      I2 => UUT_ack_count(4),
      I3 => UUT_nstate_FFd2_511,
      O => N173
    );
  UUT_out_i2cclk_mux000020_G : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => CLK_sI2C_Clk_23,
      I1 => UUT_ack_count(4),
      I2 => UUT_out_i2cclk_mux000017_532,
      O => N174
    );
  UUT_nstate_FFd1_In331 : MUXF5
    port map (
      I0 => N175,
      I1 => N176,
      S => UUT_nstate_FFd3_513,
      O => UUT_nstate_FFd1_In33
    );
  UUT_nstate_FFd1_In331_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_cmp_eq0001,
      O => N175
    );
  UUT_nstate_FFd1_In331_G : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_pstate(2),
      I1 => UUT_pstate(3),
      I2 => UUT_N32,
      I3 => UUT_Mcompar_nstate_cmp_gt0002_cy(5),
      O => N176
    );
  FPGA_Clk_BUFGP : BUFGP
    port map (
      I => FPGA_Clk,
      O => FPGA_Clk_BUFGP_29
    );
  CLK_Mcount_clk_div_lut_0_INV_0 : INV
    port map (
      I => CLK_clk_div(0),
      O => CLK_Mcount_clk_div_lut(0)
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_3_INV_0 : INV
    port map (
      I => UUT_delay_count(7),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_7_INV_0 : INV
    port map (
      I => UUT_delay_count(15),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(7)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_4_1_INV_0 : INV
    port map (
      I => UUT_delay_count(8),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_4_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_2_1_INV_0 : INV
    port map (
      I => UUT_delay_count(5),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_2_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_2_INV_0 : INV
    port map (
      I => UUT_delay_count(7),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(2)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_2_INV_0 : INV
    port map (
      I => UUT_ack_count(4),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(2)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_0_INV_0 : INV
    port map (
      I => UUT_ack_count(1),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(0)
    );
  UUT_Madd_ack_count_share0000_lut_0_INV_0 : INV
    port map (
      I => UUT_ack_count(0),
      O => UUT_Madd_ack_count_share0000_lut(0)
    );
  UUT_Madd_delay_count_share0000_lut_0_INV_0 : INV
    port map (
      I => UUT_delay_count(0),
      O => UUT_Madd_delay_count_share0000_lut(0)
    );
  UUT_Madd_writeCount_share0000_lut_0_INV_0 : INV
    port map (
      I => UUT_writeCount(0),
      O => UUT_Madd_writeCount_share0000_lut(0)
    );
  CLK_sI2C_Clk_not00011_INV_0 : INV
    port map (
      I => CLK_sI2C_Clk_23,
      O => CLK_sI2C_Clk_not0001
    );
  UUT_out_i2cclk_mux000021 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(3),
      I3 => UUT_ack_count(5),
      O => UUT_out_i2cclk_mux000021_536
    );
  UUT_out_i2cclk_mux00002_f5 : MUXF5
    port map (
      I0 => N0,
      I1 => UUT_out_i2cclk_mux000021_536,
      S => UUT_nstate_FFd1_509,
      O => UUT_out_i2cclk_mux00002
    );
  UUT_counter_mux0000_4_1_SW0 : LUT2_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_ClkRisingEdge_147,
      LO => N01
    );
  UUT_delay_count_or00001 : LUT2_D
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd1_509,
      LO => N177,
      O => UUT_delay_count_or0000
    );
  UUT_Dir_mux000031 : LUT2_D
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd4_515,
      LO => N178,
      O => UUT_N32
    );
  UUT_ack_count_mux0000_3_11 : LUT4_D
    generic map(
      INIT => X"4F0F"
    )
    port map (
      I0 => UUT_ClkRisingEdge_147,
      I1 => UUT_nstate_cmp_eq0006,
      I2 => UUT_N32,
      I3 => UUT_Mtridata_in_i2c_cmp_eq0000,
      LO => N179,
      O => UUT_N211
    );
  UUT_delay_count_mux0000_0_6 : LUT3_L
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => UUT_N45,
      I1 => UUT_ClkFallingEdge_145,
      I2 => UUT_delay_count(2),
      LO => UUT_delay_count_mux0000_0_6_474
    );
  UUT_counter_mux0000_0_21 : LUT4_D
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd1_509,
      I3 => UUT_nstate_FFd4_515,
      LO => N180,
      O => UUT_nstate_cmp_eq0010
    );
  UUT_delay_count_mux0000_0_181 : LUT2_L
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(6),
      LO => UUT_delay_count_mux0000_0_181_472
    );
  UUT_delay_count_mux0000_0_146 : LUT4_L
    generic map(
      INIT => X"FEFF"
    )
    port map (
      I0 => UUT_delay_count_mux0000_0_122_469,
      I1 => UUT_N331,
      I2 => UUT_delay_count_mux0000_0_117_468,
      I3 => UUT_delay_count_and0000,
      LO => UUT_delay_count_mux0000_0_146_470
    );
  UUT_Dir_mux00012_SW0 : LUT4_L
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(1),
      I2 => UUT_delay_count(10),
      I3 => UUT_delay_count(0),
      LO => N23
    );
  UUT_ack_count_mux0000_0_56 : LUT4_L
    generic map(
      INIT => X"E000"
    )
    port map (
      I0 => UUT_ClkRisingEdge_147,
      I1 => UUT_ack_count(0),
      I2 => UUT_nstate_cmp_eq0006,
      I3 => UUT_Mtridata_in_i2c_cmp_eq0000,
      LO => UUT_ack_count_mux0000_0_56_413
    );
  UUT_nstate_cmp_eq0000_SW0 : LUT2_L
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => UUT_counter(3),
      I1 => UUT_counter(2),
      LO => N25
    );
  UUT_Mtridata_in_i2c_mux000031_SW0 : LUT4_L
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => UUT_ack_count(1),
      I1 => UUT_N53,
      I2 => UUT_N41,
      I3 => UUT_ack_count(0),
      LO => N27
    );
  UUT_out_i2cclk_mux0000145 : LUT4_L
    generic map(
      INIT => X"AAA8"
    )
    port map (
      I0 => UUT_out_i2cclk_mux0000142_530,
      I1 => UUT_out_i2cclk_mux000071_543,
      I2 => UUT_out_i2cclk_mux000083_544,
      I3 => UUT_out_i2cclk_mux0000115_529,
      LO => UUT_out_i2cclk_mux0000145_531
    );
  UUT_out_i2cclk_mux0000270 : LUT4_L
    generic map(
      INIT => X"FF32"
    )
    port map (
      I0 => UUT_out_i2cclk_mux0000237_539,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_out_i2cclk_mux0000213_538,
      I3 => UUT_out_i2cclk_mux0000210_537,
      LO => UUT_out_i2cclk_mux0000270_540
    );
  UUT_writeCount_mux0000_10_11 : LUT4_D
    generic map(
      INIT => X"F4F0"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => UUT_delay_count_or0001,
      I2 => UUT_delay_count_or0000,
      I3 => UUT_N13,
      LO => N181,
      O => UUT_N11
    );
  UUT_Mtridata_in_i2c_cmp_eq00001 : LUT3_D
    generic map(
      INIT => X"40"
    )
    port map (
      I0 => UUT_ack_count(0),
      I1 => UUT_N70,
      I2 => UUT_ack_count_and0025,
      LO => N182,
      O => UUT_Mtridata_in_i2c_cmp_eq0000
    );
  UUT_Mtridata_in_i2c_cmp_eq0003 : LUT4_D
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => UUT_ack_count(6),
      I1 => UUT_ack_count(3),
      I2 => N31,
      I3 => UUT_ack_count_and0025,
      LO => N183,
      O => UUT_Mtridata_in_i2c_cmp_eq0003_336
    );
  UUT_Mtridata_in_i2c_not0001134 : LUT3_L
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_ack_count(6),
      I2 => UUT_ack_count(3),
      LO => UUT_Mtridata_in_i2c_not0001134_345
    );
  UUT_Mtridata_in_i2c_not0001176 : LUT4_L
    generic map(
      INIT => X"FFA8"
    )
    port map (
      I0 => UUT_Mtridata_in_i2c_not0001162_347,
      I1 => UUT_Mtridata_in_i2c_not0001137_346,
      I2 => UUT_Mtridata_in_i2c_not000185_352,
      I3 => UUT_Mtridata_in_i2c_not000137_349,
      LO => UUT_Mtridata_in_i2c_not0001176_348
    );
  UUT_Dir_mux000051 : LUT3_D
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => UUT_ack_count(9),
      I1 => UUT_ack_count(10),
      I2 => UUT_ack_count(11),
      LO => N184,
      O => UUT_N41
    );
  UUT_nstate_cmp_eq00011 : LUT4_D
    generic map(
      INIT => X"0800"
    )
    port map (
      I0 => UUT_ack_count(8),
      I1 => UUT_ack_count(0),
      I2 => UUT_N41,
      I3 => UUT_N42,
      LO => N185,
      O => UUT_nstate_cmp_eq0001
    );
  UUT_Dir_mux0000421 : LUT4_D
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => UUT_ack_count(2),
      I1 => UUT_ack_count(1),
      I2 => UUT_ack_count(7),
      I3 => UUT_ack_count(5),
      LO => N186,
      O => UUT_N62
    );
  UUT_shiftReg_cmp_eq00032 : LUT4_D
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_delay_count(9),
      I1 => UUT_delay_count(7),
      I2 => UUT_delay_count(4),
      I3 => N33,
      LO => N187,
      O => UUT_N45
    );
  UUT_shiftReg_or00002_SW0 : LUT2_L
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => UUT_delay_count(4),
      I1 => UUT_delay_count(6),
      LO => N35
    );
  UUT_shiftReg_mux0000_5_SW0 : LUT4_L
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => UUT_shiftReg(6),
      I1 => UUT_shiftReg(4),
      I2 => UUT_N64,
      I3 => UUT_N12,
      LO => N47
    );
  UUT_shiftReg_mux0000_2_3 : LUT3_D
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0010,
      I1 => UUT_shiftReg(1),
      I2 => UUT_ClkRisingEdge_147,
      LO => N188,
      O => UUT_shiftReg_mux0000_2_3_594
    );
  UUT_shiftReg_mux0000_1_SW0 : LUT4_L
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => UUT_shiftReg(0),
      I1 => UUT_N64,
      I2 => UUT_shiftReg(2),
      I3 => UUT_N12,
      LO => N49
    );
  UUT_shiftReg_mux0000_6_3 : LUT3_L
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0010,
      I1 => UUT_shiftReg(5),
      I2 => UUT_ClkRisingEdge_147,
      LO => UUT_shiftReg_mux0000_6_3_603
    );
  UUT_shiftReg_mux0000_3_5 : LUT4_L
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0010,
      I1 => UUT_shiftReg(2),
      I2 => UUT_ClkRisingEdge_147,
      I3 => UUT_nstate_cmp_eq0005,
      LO => UUT_shiftReg_mux0000_3_5_596
    );
  UUT_shiftReg_mux0000_0_5 : LUT4_L
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0010,
      I1 => UUT_ClkRisingEdge_147,
      I2 => UUT_out_i2c,
      I3 => UUT_nstate_cmp_eq0005,
      LO => UUT_shiftReg_mux0000_0_5_589
    );
  UUT_shiftReg_or000012 : LUT2_L
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => UUT_delay_count(0),
      I1 => UUT_delay_count(6),
      LO => UUT_shiftReg_or000012_607
    );
  UUT_shiftReg_or000047 : LUT4_D
    generic map(
      INIT => X"FFEC"
    )
    port map (
      I0 => UUT_delay_count(10),
      I1 => UUT_shiftReg_or000032_609,
      I2 => UUT_shiftReg_or000017_608,
      I3 => UUT_N331,
      LO => N189,
      O => UUT_shiftReg_or0000
    );
  UUT_Mtridata_in_i2c_mux000011 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => UUT_Mtridata_in_i2c_334,
      I2 => UUT_shiftReg(0),
      LO => UUT_Mtridata_in_i2c_mux000011_338
    );
  UUT_Mtridata_in_i2c_mux000065 : LUT4_L
    generic map(
      INIT => X"F080"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0000,
      I1 => UUT_Mtridata_in_i2c_mux000037_340,
      I2 => UUT_delay_count_or0001,
      I3 => UUT_Mtridata_in_i2c_mux000022_339,
      LO => UUT_Mtridata_in_i2c_mux000065_341
    );
  UUT_shiftReg_cmp_eq00031_SW0 : LUT4_D
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_delay_count(13),
      I1 => UUT_delay_count(12),
      I2 => UUT_delay_count(11),
      I3 => UUT_delay_count(14),
      LO => N190,
      O => N51
    );
  UUT_shiftReg_mux0000_0_240 : LUT4_L
    generic map(
      INIT => X"80C0"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_N60,
      I3 => UUT_N13,
      LO => UUT_shiftReg_mux0000_0_240_587
    );
  UUT_shiftReg_mux0000_0_223 : LUT4_L
    generic map(
      INIT => X"EAAA"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => N56,
      I2 => UUT_shiftReg_cmp_eq0001,
      I3 => UUT_N38,
      LO => UUT_N33_376
    );
  UUT_out_i2cclk_mux000081_SW0 : LUT4_L
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_ack_count(10),
      I1 => UUT_ack_count(11),
      I2 => UUT_ack_count(2),
      I3 => UUT_ack_count(1),
      LO => N64
    );
  UUT_shiftReg_cmp_eq00031_SW1 : LUT3_L
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => UUT_delay_count(15),
      I1 => UUT_delay_count(3),
      I2 => UUT_delay_count(2),
      LO => N68
    );
  UUT_shiftReg_mux0000_0_1311_SW0 : LUT4_L
    generic map(
      INIT => X"A2A0"
    )
    port map (
      I0 => UUT_shiftReg(7),
      I1 => UUT_ClkFallingEdge_145,
      I2 => UUT_shiftReg_mux0000_0_110_582,
      I3 => UUT_shiftReg_mux0000_0_116_584,
      LO => N70
    );
  UUT_shiftReg_mux0000_0_1311_SW3 : LUT4_L
    generic map(
      INIT => X"FAF2"
    )
    port map (
      I0 => UUT_shiftReg(4),
      I1 => UUT_ClkFallingEdge_145,
      I2 => UUT_shiftReg_mux0000_4_3_600,
      I3 => UUT_shiftReg_mux0000_0_110_582,
      LO => N74
    );
  UUT_shiftReg_mux0000_0_1311_SW5 : LUT4_L
    generic map(
      INIT => X"FAF2"
    )
    port map (
      I0 => UUT_shiftReg(2),
      I1 => UUT_ClkFallingEdge_145,
      I2 => UUT_shiftReg_mux0000_2_3_594,
      I3 => UUT_shiftReg_mux0000_0_110_582,
      LO => N77
    );
  UUT_Mtrien_in_i2c_mux0000210_SW0 : LUT2_L
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0001,
      I1 => UUT_shiftReg_cmp_eq0000,
      LO => N79
    );
  UUT_N362 : LUT4_L
    generic map(
      INIT => X"A2AA"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0006,
      I1 => UUT_N70,
      I2 => UUT_ack_count(0),
      I3 => UUT_ack_count_and0025,
      LO => UUT_N362_382
    );
  UUT_Dir_mux00002 : LUT4_D
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_N351,
      I1 => UUT_N41,
      I2 => UUT_ack_count(7),
      I3 => N83,
      LO => N191,
      O => UUT_N27
    );
  UUT_shiftReg_cmp_eq00001_SW0 : LUT4_L
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => UUT_delay_count(0),
      I1 => UUT_delay_count(9),
      I2 => UUT_delay_count(7),
      I3 => UUT_delay_count(1),
      LO => N87
    );
  UUT_Mtridata_in_i2c_not000137_SW0 : LUT3_L
    generic map(
      INIT => X"7E"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_ack_count(8),
      I2 => UUT_ack_count(0),
      LO => N91
    );
  UUT_N320 : LUT4_L
    generic map(
      INIT => X"F272"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(6),
      I3 => UUT_N332,
      LO => UUT_N320_374
    );
  UUT_N392_SW0 : LUT4_L
    generic map(
      INIT => X"2F2E"
    )
    port map (
      I0 => UUT_ack_count(7),
      I1 => UUT_ack_count(6),
      I2 => UUT_ack_count(8),
      I3 => UUT_ack_count(5),
      LO => N93
    );
  UUT_N3157 : LUT4_L
    generic map(
      INIT => X"15FF"
    )
    port map (
      I0 => UUT_ack_count(5),
      I1 => N102,
      I2 => UUT_ack_count(2),
      I3 => UUT_ack_count(7),
      LO => UUT_N3157_371
    );
  UUT_out_i2cclk_mux0000237_SW0 : LUT3_L
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => UUT_ack_count(9),
      I1 => UUT_ack_count(8),
      I2 => UUT_ack_count(0),
      LO => N104
    );
  UUT_Dir_mux0000611_SW0 : LUT4_L
    generic map(
      INIT => X"8100"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_ack_count(8),
      I2 => UUT_ack_count(0),
      I3 => UUT_N72,
      LO => N106
    );
  UUT_ack_count_mux0000_0_23 : LUT4_L
    generic map(
      INIT => X"0002"
    )
    port map (
      I0 => UUT_N70,
      I1 => UUT_N41,
      I2 => UUT_ack_count(7),
      I3 => N108,
      LO => UUT_ack_count_mux0000_0_23_411
    );
  UUT_Mtridata_in_i2c_not000155 : LUT4_L
    generic map(
      INIT => X"EC20"
    )
    port map (
      I0 => UUT_nstate_FFd1_509,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_nstate_FFd3_513,
      LO => UUT_Mtridata_in_i2c_not000155_350
    );
  UUT_nstate_FFd4_In77 : LUT4_L
    generic map(
      INIT => X"8A02"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_cmp_eq0001,
      I3 => UUT_Mcompar_nstate_cmp_gt0002_cy(7),
      LO => UUT_nstate_FFd4_In77_518
    );
  UUT_N3106_SW0 : LUT4_L
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => UUT_ack_count(1),
      I1 => UUT_ack_count(4),
      I2 => UUT_ack_count(3),
      I3 => UUT_ack_count(0),
      LO => N119
    );
  UUT_Dir_mux000011_SW0 : LUT4_L
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => UUT_ack_count(8),
      I1 => UUT_ack_count(1),
      I2 => UUT_nstate_FFd1_509,
      I3 => UUT_ack_count(0),
      LO => N125
    );
  UUT_shiftReg_mux0000_0_116 : LUT4_D
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_nstate_FFd4_515,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_N13,
      LO => N192,
      O => UUT_shiftReg_mux0000_0_116_584
    );
  UUT_writeCount_mux0000_10_21 : LUT4_D
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => UUT_ClkFallingEdge_145,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_N32,
      I3 => UUT_N13,
      LO => N193,
      O => UUT_N35
    );
  UUT_Dir_mux0000127 : LUT3_L
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => UUT_N27,
      I1 => UUT_nstate_FFd3_513,
      I2 => UUT_nstate_FFd1_509,
      LO => UUT_Dir_mux0000127_151
    );
  UUT_shiftReg_mux0000_7_SW0_SW0 : LUT3_L
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => UUT_nstate_cmp_eq0010,
      I1 => UUT_ClkRisingEdge_147,
      I2 => UUT_shiftReg(6),
      LO => N132
    );
  UUT_Dir_mux000062 : LUT3_D
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => UUT_nstate_FFd2_511,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd3_513,
      LO => N194,
      O => UUT_nstate_cmp_eq0011
    );
  UUT_ack_count_mux0000_10_212 : LUT4_L
    generic map(
      INIT => X"1000"
    )
    port map (
      I0 => UUT_ack_count(0),
      I1 => N136,
      I2 => UUT_N70,
      I3 => UUT_ack_count_and0025,
      LO => UUT_ack_count_mux0000_10_212_416
    );
  UUT_delay_count_mux0000_11_1_SW1 : LUT4_L
    generic map(
      INIT => X"0008"
    )
    port map (
      I0 => UUT_N45,
      I1 => UUT_N32,
      I2 => UUT_delay_count(2),
      I3 => UUT_ClkFallingEdge_145,
      LO => N140
    );
  UUT_Dir_mux0000194_SW0_SW2 : LUT4_L
    generic map(
      INIT => X"FFAB"
    )
    port map (
      I0 => UUT_Dir_mux0000148_153,
      I1 => UUT_nstate_FFd4_515,
      I2 => UUT_nstate_FFd2_511,
      I3 => UUT_Dir_mux0000143_152,
      LO => N143
    );
  UUT_shiftReg_mux0000_0_110_SW1 : LUT3_L
    generic map(
      INIT => X"26"
    )
    port map (
      I0 => UUT_nstate_FFd3_513,
      I1 => UUT_nstate_FFd2_511,
      I2 => UUT_ClkRisingEdge_147,
      LO => N145
    );

end Structure;

